Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2003-04-08
2004-09-21
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
75, 75, 75, 75, 75, 75, 75
Reexamination Certificate
active
06794693
ABSTRACT:
The present application is based on Japanese priority application No. 2002-250933 filed on Aug. 29, 2002 with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device that contains a MOS (Metal Oxide Semiconductor) transistor, and especially relates to a semiconductor device wherein change of threshold voltage with time and degradation of drain saturation current with time are prevented from occurring.
2. Description of the Related Art
In recent years and continuing, miniaturization of semiconductor elements and multilayer wiring is progressing, resulting in miniaturization of semiconductor devices and high-density integration of the semiconductor elements. Further, improvements in the operating speed of semiconductor devices are required.
However, where wiring width and wiring interval are made narrow for high-density integration, RC delay arises due to increases in wiring resistance (R) and wiring capacitance (C), which set a limit to the improvements of the operating speed.
Then, in order to minimize the RC delay, reduction of the wiring resistance has been practiced, using a dual damascene process (Cu dual damascene process) that uses Cu as the wiring material. The dual damascene process forms a slot for wiring and a contact hole in one body in an inter-layer insulation layer, and embeds Cu in the slot and the contact hole for electrically connecting layers. In this manner, the wiring resistance can be reduced and the RC delay can be reduced by using low resistance Cu, in comparison with the conventional wiring structure using aluminum.
FIG. 1
is a sectional figure showing a MOS device
10
that has a Cu dual damascene structure. With reference to
FIG. 1
, the MOS device
10
includes a semiconductor substrate
11
of a single conductivity type, for example, an n-type semiconductor substrate, which further includes a device isolation region
12
that is formed by an STI (Shallow Trench Isolation) process, a device region
13
surrounded by the device isolation region
12
, a gate insulating film
15
formed at the device region
13
on the semiconductor substrate
11
, a gate electrode
16
, a side wall insulating film
14
supported by the gate electrode
16
, and a source region
20
and a drain region
21
that are composed of an opposite conductivity type dopant ion diffused in the semiconductor substrate
11
, a multilayer wiring structure
22
of a Cu dual damascene structure formed on the semiconductor substrate
11
, a passivation layer
23
, etc.
The multilayer wiring structure
22
further includes a first wiring layer
24
, a plug
25
that connects the first wiring layer
24
to a second wiring layer
24
and the gate electrode
16
to the second wiring layer
24
, inter-layer insulation layers
26
that insulate the first and the second wiring layers
24
, respectively, an etching stopper layer
30
used when forming the wiring layers
24
and the plug
25
, a Cu diffusion prevention layer
31
, etc.
Here, the inter-layer insulation layer
26
is constituted by a silicon oxide film, a low dielectric constant insulating film, etc. that are formed by the CVD method (chemical vapor deposition) and the like. Further, the etching stopper layer
30
is constituted by a silicon nitride film formed by a sputtering method, the CVD method, and the like.
FIG. 2
is a sectional figure showing a MOS device
40
that includes an aluminum wiring structure
41
. With reference to
FIG. 2
, the aluminum wiring structure
41
includes a wiring layer
42
, a plug
43
, and an inter-layer insulation layer
44
that surrounds the wiring layer
42
and the plug
43
.
In the aluminum wiring structure
41
, an etching stopper layer is not prepared on the surface of the inter-layer insulation layer
44
, which is different from the multilayer wiring structure
22
of Cu dual damascene. Here, the MOS transistor portion is the same as that of FIG.
1
.
With a p-channel MOS transistor that has a Cu dual damascene structure as shown in
FIG. 1
, there is a problem in that threshold voltage changes with time and drain saturation current degrades with time. Details will be explained below.
FIG. 3
shows degradation with time of the drain saturation current &Dgr;Ids of the p-channel MOS transistor that has the Cu dual damascene structure as shown in
FIG. 1
, (indicated as “Cu wiring structure” in
FIG. 3
) and an aluminum wiring structure as shown in FIG.
2
. In
FIG. 3
, stress time expresses the elapsed time of the MOS transistor being energized. Here, the voltage applied to the gate is a constant.
With reference to
FIG. 3
, the time for the drain saturation current to be degraded by 5% is considered, which is 3×10
4
seconds in the case of the aluminum wiring structure, and about 1×10
3
seconds in the case of the Cu dual damascene structure. That is, the Cu dual damascene structure is more susceptible to the degradation. This phenomenon is called NBTI (Negative Bias Temperature Instability). Specifically, if moisture invades into a gate insulating film, a trap is formed in the gate insulating film, and the trap easily catches an electron hole, which is a carrier. In this manner, the number of carriers that are caught by the trap increases with the progress of the stress time of the MOS transistor, causing the threshold voltage to change with time, and the drain saturation current to decrease with time.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a semiconductor device, wherein degradation of the drain saturation current with time of a MOS transistor and change of threshold voltage with time are prevented from occurring, and the manufacturing method thereof, that substantially obviate one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description that follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor device and a manufacturing method thereof particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides the semiconductor device as follows.
The semiconductor device of the present invention includes a MOS transistor formed on a semiconductor substrate, and a multilayer wiring structure formed on the semiconductor substrate and connected to the MOS transistor. The multilayer wiring structure includes an inter-layer insulating film, a permeable insulating film formed on the surface of the inter-layer insulating film, and a conductive pattern.
The permeable insulating film facilitates discharge of moisture that may be contained in the inter-layer insulating film made of silicon oxide formed by the plasma CVD method and the like. By discharging the moisture to the outside through the permeable insulating film, the moisture is prevented from invading the gate insulating film. Accordingly, the change with time of threshold voltage and degradation with time of the drain saturation current of the MOS transistor are prevented.
Here, the permeable insulating film may be made from silicon carbide that has high moisture permeability and efficiently discharges the moisture, as will be explained later in reference to FIG.
6
.
The inter-layer insulating film may be an organic film that has a low dielectric constant.
Alternatively, the inter-layer insulating film can be structured by a lamination of a low dielectric constant organic film and
Kakamu Katsumi
Suzuki Atsushi
Tabuchi Kiyotaka
Clark Jasmine
Fujitsu Limited
Westerman Hattori Daniels & Adrian LLP
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