Semiconductor device and manufacturing method thereof

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S287000, C438S484000, C438S585000

Reexamination Certificate

active

06787451

ABSTRACT:

FIELD OF THE INVENTION
This invention concerns a semiconductor device and a manufacturing method thereof and, more in particular, it relates to a semiconductor device having a field effect transistor in which a high dielectric film is applied to a gate insulation film for use in a field effect transistor, as well as a manufacturing method thereof.
BACKGROUND OF THE INVENTION
MOS transistors as a basic constituent circuit for large scale integrated circuits (LSI) have been highly integrated in accordance with a scaling rule. However, it is considered that the gate insulation film using silicon dioxide (SiO
2
) is limited to a film thickness of 2.0 nm or less at the cost of increasing the consumption power and lowering reliability of the insulation film due to increase a direct tunnel leakage current. Further, since a diffusion barrier to impurities is weakened in such thin SiO
2
, it brings about leakage of impurities from a gate electrode. Further, a stringent production control is necessary for mass production of thin SiO
2
films at a good uniformity.
In view of the above, for attaining further refinement and higher operation speed of the device simultaneously and breaking through the limit for the scaling, development for “High Dielectric Constant (high-K) Material” capable of obtaining a field effect performance equal to or superior to SiO
2
even when it is formed with a thickness larger than SiO
2
has been conducted actively. Potential candidate materials include IV group oxides such as zirconia (ZrO
2
), hafnia (HfO
2
), III group oxides such as alumina (Al
2
O
3
) and yttria (Y
2
O
3
) and silicates as solid solutions of such metal oxides and SiO
2
. The group IV oxides and group III oxides are materials utilized as the gate insulation film in the early stage of Si semiconductors. However, after the technique for forming the gate insulation film with SiO
2
has been established, SiO
2
has been used exclusively in view of its excellent characteristics. For example, a field effect transistor (FET) using ZrO
2
for the gate insulation film is described in IEDM' 99 Tech. Digest, pp. 145, 1999. A field effect transistor using HfO
2
for the gate insulation film is described in 2000 Symposium on VLSI Technology Digest of Technical Papers, and a field effect transistor using alumina for the gate insulation film is described in IEDM' 00 Tech. Digest pp. 145, 2000. A method for manufacturing a metal silicate is described in JP-A-135774/1999.
Existing FET forming processes include, after forming the gate insulation film, a step of depositing a gate comprising, for example, polycrystalline silicon, a step of injecting impurities to the polycrystalline silicon gate, a step of fabricating the gate, a step of injecting impurities to a source-drain region, and a heating step of activating the impurities. Particularly, for the heating step (activating the impurities), a temperature of 900° C. or higher is desirable for controlling to a predetermined impurity profile. Accordingly, it is necessary for the gate insulation film comprising the high dielectric material to maintain interface characteristics at high quality even by the FET forming process including the heating step.
However, in a case of forming FET, for example, by applying Al
2
O
3
to a gate insulation film, the following problems exist as described in IEDM' 00 Tech. Digest, pp 145. Since negative fixed charges are present in the insulation film, a flat band voltage of an N channel type MISFET shifts by 0.3 V or more toward a positive voltage and a threshold voltage of FET also changes. Further, since the mobility of electrons is small which is about ¼ compared with a universal curve of an SiO
2
film (general curve giving effective field effect dependence of mobility), the source-drain current upon operating FET can not be increased as expected. One of the reasons that the mobility of electrons is small is attributable to scattering of electrons in the channel because of the presence of negative fixed charges in the insulation film. Accordingly, for applying Al
2
O
3
to the gate insulation film, it is necessary to remove the negative fixed charges in the insulation film.
The equivalent SiO
2
thickness (EOT) of a high dielectric gate insulation film is defined as below. When the thickness of an SiO
2
gate insulation film obtained by fixing a refractive index to 1.46 is t
OX
measured by an ellipsometer using a light at frequency of 784 nm, the SiO
2
equivalent film thickness (EOT) of the high dielectric gate insulation film having an identical electrical capacitance with that of an MOS capacitor formed by using the SiO
2
gate insulation film.
This invention intends to develop a high dielectric insulation film at high quality with less SiO
2
equivalent film thickness, less leakage current when compared by an identical equivalent film thickness, stable also to thermal load in the FET forming process and excellent in the boundary characteristics.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the semiconductor device has a field effect transistor formed on a silicon substrate stacked with a metal oxide film having a higher dielectric constant than that of a silicon oxide film, and a gate insulation film with an SiO
2
equivalent thickness of 2.0 nm or less, wherein the gate insulation film comprises a first silicon oxide film or a silicon oxynitride film of a thickness of 0.5 nm or more formed between the silicon substrate and the metal oxide film.
According to another aspect of the invention, the method for manufacturing a semiconductor device having a field effect transistor in which a metal oxide film of a higher dielectric constant than that of a silicon oxide film formed on a silicon substrate is used as a gate insulation film, comprises: forming the metal oxide film on the silicon substrate; and forming a first silicon oxide film or a silicon oxynitride film with a thickness of 0.5 nm or more between the silicon substrate and the metal oxide film by a heat treatment in an oxidative atmosphere at a temperature higher than a source-drain activating temperature for forming the field effect transistor; and forming a gate of the field effect transistor on the metal oxide film after the heat treatment.
According to a third aspect of the invention, the method for manufacturing a semiconductor device having a field effect transistor in which a metal oxide film of a higher dielectric constant than that of a silicon oxide film formed on a silicon substrate is used as a gate insulation film, comprising: forming a silicon oxide film or a silicon oxynitride film with a thickness of 0.5 nm or more on the silicon substrate by a heat treatment in an oxidative atmosphere at a temperature higher than a source-drain activating temperature for forming the field effect transistor; forming a metal oxide film on the silicon oxide film or the silicon oxynitride film after the heat treatment; and forming a gate of the field effect transistor on the metal oxide film.


REFERENCES:
patent: 2002/0050608 (2002-05-01), Landheer et al.
Laegu Kang, Yongjoo Jeon, Katsunori Onishi, Byoung Hun Lee, Wen-Jie Qi, Renee Nieh, Sundar Gopalan and Jack C. Lee, “Single-layer Thin HfO2Gate Dielectric with n+—Polysilicon Gate” , 2000 Symposium on VLSI Technology Digest of Technical Papers, p. 2.
Seiichi Iwata and Akitoshi Ishizaka, “Electron Spectroscopic Analysis of the SiO2/Si System and Correlation with Metal-Oxide-Semiconductor Device Characteristics”, J. Appl. Phys., vol. 79, No. 9, May 1, 1996, pp. 6653-6713.
D.A. Buchanan, E.P. Gusev, E. Cartier, H. Okorn-Schmidt, K. Rim, M.A. Gribelyuk, A. Mocuta, A. Ajmera, M. Copel, S. Guha, N. Borjarczuk, A. Callegari, C. D'Emie, P. Kozlowski, K. Chan, R. J. Fleming, P.C. Jamison, J. Brown, R. Amdi, “80 nm Poly-Silicon gated n-FETs with Ultra-Thin A12O3Gate Dielectric for ULSI Applications”, 2000 IEEE, pp. 2-3.
Wen-Jie Qi, Renee Nieh, Byoung Hun Lee, Laegu Kang, Yongjoo Jeon, Katsunori Onishi, Tat Ngai, Sanjay Banerjee and Jack C. Lee, “MOSCAP and MOSFET Chara

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method thereof will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3200290

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.