Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-29
2004-01-06
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06674114
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and manufacturing method thereof and, more particularly, a structure of and manufacturing method of a CMOS transistor in a CMOS process using the LOCOS technique.
Explanation is made below on the conventional semiconductor device and manufacturing method thereof, with reference to the drawings.
In
FIG. 19
, numeral
51
denotes a semiconductor substrate (P-sub), wherein an N type well (NW)
52
and a P type well (PW)
53
are formed in the substrate
51
. A first (P-channel) MOS transistor is constituted to have a first gate electrode
55
A formed on the N type well
52
through a first gate oxide film
54
A and first (P type) source/drain regions
56
formed in the vicinity of the gate electrode
55
A. A second (N-channel) MOS transistor is constituted to have a second gate electrode
55
B formed on the P type well
53
through a second gate oxide film
54
B and second (N type) source/drain regions
57
formed in the vicinity of the gate electrode
55
B. Meanwhile, numeral
58
denotes a device isolation film.
Explained in the below is a method of manufacturing a semiconductor device in the above. At first, a pad oxide film
60
and silicon nitride film
61
is formed in a predetermined region (region for a P type well
53
) on the semiconductor substrate
51
, as shown in FIG.
20
. Thereafter, using the pad oxide film
60
and silicon nitride film
61
as a mask, phosphorus ion (
31
P
+
), for example, is ion-implanted to the substrate surface to form an ion-implant region
62
.
Subsequently, as shown in
FIG. 21
, the silicon nitride film
61
is used as a mask to oxidize the substrate surface by a LOCOS technique thereby forming a LOCOS film
63
. At this time, the phosphorus ion implanted in the region beneath the LOCOS film
63
is diffused toward the inward of the substrate thus forming an N type region
64
.
Next, as shown in
FIG. 22
, the pad oxide film
60
and silicon nitride film
61
is removed away. Thereafter, the LOCOS film
63
is used as a mask to ion-implant boron ion (
11
B
+
) to the substrate surface thereby forming an ion-implant region
65
.
Then, as shown in
FIG. 23
, after removing the LOCOS film
63
, the impurity ions implanted in the substrate
51
are thermally diffused to form an N type well
52
and a P type well
53
.
Subsequently, as shown in
FIG. 24
, after forming a device isolation film
58
in the border at between the N type well
52
and the P type well
53
, a gate oxide film
54
is formed on the other region than the device isolation film
58
to form thereon a conductor film
55
. Furthermore, by patterning the conductor film
55
, a first gate electrode
55
A is formed on the N type well
52
through a first gate oxide film
54
A and, similarly, a second gate electrode
55
B is formed on the P type well
53
through a second gate oxide film
54
B.
Then, in the state that a resist film is formed on the region for a second MOS transistor, ion is implanted through the first gate electrode
55
A as a mask. Thus, P type source/drain regions
56
are formed in the vicinity of the first gate electrode
55
A thereby constituting a first MOS transistor. N type source/drain regions
57
are formed in the vicinity of the second gate electrode
55
B thereby constituting a second MOS transistor.
Herein, the above CMOS structure utilizes the LOCOS technique in order to separately form the N type well
52
and the P type well
53
. Consequently, the N type well
52
formed in the region removed of the LOCOS film
53
is lower in position than the P type well
53
(see FIG.
23
).
Accordingly, in the region such a step is caused as shown in
FIG. 24
, when the conductor film
55
on the gate oxide film
54
is patterned to form a gate electrode, an organic thin film
66
(BARC: Bottom Anti-Reflection Coating) is applied as a reflection preventing film beneath a resist film
67
in order to prevent linewidth variation due to the standing wave or halation in the step.
However, the organic BARC, applied by spin coating, has a thickness increased in the step lower region and decreased in the step higher region (see FIG.
24
). Consequently, where working a precise BARC (e.g. 0.35 &mgr;m) by dry etching, a variation in linewidth occurs between the gate electrode on the step lower region and the gate electrode on the step higher region due to the difference in BARC thickness at between the step lower region and the step higher region. Incidentally,
FIG. 25
shows the state that the BARC is left in the step lower region due to insufficient amount of BARC etching (the organic thin film
66
A and the organic thin film
66
B equivalent in width) whereas
FIG. 26
shows the state that there is a variation in linewidth caused between the gate electrodes due to a difference in BARC etch amount (the organic thin film
66
D is smaller in width as compared to the organic thin film
66
C (removal amount on the organic thin film
66
: X
1
<X
2
)).
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made in view of the foregoing problem, which comprises, in a semiconductor device having one-conductivity type and opposite-conductivity type semiconductor regions formed having a step as a border on a one-conductivity type semiconductor substrate, a first transistor having a first linewidth in either a semiconductor region in one conductivity type or a semiconductor region in opposite conductivity type formed in a step lower region; and a second transistor having a second linewidth greater than a linewidth of the first transistor in either the one-conductivity type semiconductor region or the opposite-conductivity type semiconductor region formed in a step higher region.
Meanwhile, a method of manufacturing the same comprises: a step of forming a first gate oxide film on either a one-conductivity type semiconductor region or an opposite-conductivity type semiconductor region formed in a step lower region; a step of forming a second gate oxide film on either the one-conductivity type semiconductor region or the opposite-conductivity type semiconductor region formed in a step higher region; a step of forming a conductor film on the first and second oxide films and, thereafter, patterning the conductor film to form a first gate electrode and a second gate electrode greater in linewidth than the first gate electrode; a step of forming a first source/drain region in the vicinity of the first gate electrode to have an opposite conductivity type to the semiconductor region forming the gate electrode thereby forming a first transistor; and a step of forming a second source/drain region in the vicinity of the second gate electrode to have an opposite conductivity type to the semiconductor region forming the gate electrode thereby forming a second transistor.
The first transistor constitutes a MOS transistor of normal withstand voltage (hereinafter, a normal-voltage MOS transistor) and the second MOS transistor constitutes a MOS transistor of high withstand voltage (hereinafter, a high-voltage MOS transistor).
Meanwhile, the step of forming one-conductivity type and opposite-conductivity type semiconductor regions in the one-conductivity type substrate utilizes a LOCOS technique thereby forming a step on the substrate.
Furthermore, the step of patterning the conductor film to form first and second gate electrodes includes patterning the organic film through the resist film as a mask after forming an organic film and resist film on the conductor film and, further, patterning the conductor film through the resist film and organic film as a mask.
Due to this, in the case that there is a step on the substrate, in the step lower region is formed a first gate electrode smaller in linewidth than the second gate electrode formed in the step higher region, making possible to cope with a precise gate electrode less in working margin.
REFERENCES:
patent: 4975756 (1990-12-01), Haken et al.
patent: 5998843 (1999-12-01), Yoshida
patent: 6143594 (2000-11-01), Tsao et al.
pat
Ishibe Shinzo
Mori Shinya
Suzuki Akira
Taniguchi Toshimitsu
Fish & Richardson P.C.
Le Thao P
Nelms David
Sanyo Electric Co,. Ltd.
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