Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-14
2003-11-11
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S681000
Reexamination Certificate
active
06645859
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof which allow successful gap filling with an insulating film between interconnections placed for electrically connecting semiconductor elements on a semiconductor substrate, and further prevent cracking or chipping of the interconnections that would otherwise occur when filling the insulating film.
2. Description of the Background Art
In a semiconductor device, interconnections, especially aluminum interconnections, are used for electrically connecting semiconductor elements formed on a semiconductor substrate with each other. In the semiconductor devices of recent years having narrow gaps or valleys between the interconnections, chemical vapor deposition utilizing high-density plasma (hereinafter, HDP-CVD: High Density Plasma-Chemical Vapor Deposition) is employed for formation of an insulating film to fill in the gaps between the interconnections.
FIG. 7
is a cross sectional view showing aluminum interconnections
103
in a conventional semiconductor device, that are placed on an interlayer insulating film
101
formed on a semiconductor substrate. Referring to
FIG. 7
, a Ti/TiN film
102
is formed beneath aluminum interconnection
103
as its under layer. Formed on aluminum interconnection
103
is a Ti/TiN film
104
as its top layer. The top layer Ti/TiN film
104
functions as an anti-reflective film at the time of interconnection patterning. The under layer Ti/TiN film
102
is provided to improve tolerance to stress migration and electric migration of the aluminum interconnection.
Aluminum interconnections
103
are covered with an insulating film (hereinafter, also referred to as “HDP insulating film”)
106
formed by HDP-CVD. Formed on HDP insulating film
106
is an insulating film
107
, which is deposited by a method other than HDP-CVD. Formation of insulating film
107
by HDP-CVD would cause damage to the insulating film
106
, since sputtering is carried out at the same time as film deposition during HDP-CVD, as will be described later.
According to the manufacturing method as described above, at the time of interconnection patterning, the Ti/TiN films project outward from the sidewalls of the aluminum interconnections, due to their different etching characteristics, so that eaves, or overhangs, are created. In the subsequent HDP-CVD, high-density plasma and substrate bias are utilized in combination. With strong directivity of the film species in a vertical direction, film deposition and sputtering are carried out simultaneously. Since the top layer Ti/TiN film has the overhangs projecting outward from the upper edges of the aluminum interconnection, voids are likely to occur beneath the overhangs (in the areas denoted by “D” in FIG.
7
), resulting in insufficient gap filling. In addition, during the HDP-CVD, the aluminum interconnection tends to suffer deformation due to the sputtering. It is highly possible that a crack or chip appears on the aluminum interconnection, e.g., in the area denoted by “E” in FIG.
7
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof by which, when filling an insulating film between interconnections by HDP-CVD, even if a Ti/TiN film serving as an anti-reflective film at the time of interconnection patterning is projecting from upper edges of each interconnection, voids beneath such overhangs as well as chips or cracks in the interconnections are prevented.
The manufacturing method of a semiconductor device according to an aspect of the present invention includes the steps of: forming semiconductor elements on a semiconductor substrate; forming on the semiconductor elements a plurality of interconnections side by side for electrically connecting the semiconductor elements with each other, each interconnection having a top protective layer on top surface thereof; forming a protective insulating film, by chemical vapor deposition (CVD) other than high density plasma-chemical vapor deposition (HDP-CVD), to cover top and side surfaces of the interconnections and a bottom surface of a gap between the interconnections; and forming an insulating film, by HDP-CVD, to cover the protective insulating film as well as to fill in the gap between the interconnections covered with the protective insulating film.
With this method, even if the top protective layer is projecting outward from the upper edges of the interconnection, it is possible to use CVD, with characteristic small directivity in the vertical direction, to deposit the protective insulating film without voids beneath such overhangs. In addition, even if the temperature increases during the film deposition by HDP-CVD, the protective insulating film covering the interconnections prevents cracking or chipping thereof due to such temperature increase.
CVD other than HDP-CVD includes parallel plate type plasma CVD, thermal CVD, and others. Assuming that the semiconductor elements are semiconductor element regions formed in the semiconductor substrate, the interconnections may be formed on the semiconductor substrate in contact therewith, or they may be formed on an upper-level, interlayer insulating film in contact therewith. A Ti/TiN film, for example, may be employed as the top protective layer.
In the step of forming the protective insulating film in the method of the present invention, at least one of SiO
2
film, SiON film, Si
3
N
4
film and fluorine-containing SiO
2
film may be formed as the protective insulating film using TEOS (Tetra-Ethyl-Ortho-Silicate) as a raw material.
With this configuration, it is possible to cover the interconnections with the protective insulating film exhibiting excellent coverage quality.
In the relevant step of forming the protective insulating film, the protective insulating film is preferably deposited at a temperature of not greater than 400° C.
With this configuration, even if the interconnections are made of aluminum, cracking or chipping of the aluminum is prevented.
In the step of forming the insulating film by HDP-CVD in the method of the present invention, conditions on film deposition may be differentiated between its initial stage and the subsequent stage. Specifically, in the initial stage, the insulating film is deposited under a condition encouraging more intensive sputtering than in ordinary HDP-CVD. Thus, the film deposition proceeds while the protective insulating film covering the upper portions of the interconnections is sputter etched to widen the opening between the neighboring interconnections. In the subsequent stage, the insulating film is deposited under a condition allowing less intensive sputtering than in the initial stage.
With such a configuration, it is possible, without increasing the number of process steps, to fill in the gap between the interconnections while widening the opening narrowed by the formation of the protective insulating film. This prevents gap filling failure between the interconnections.
In the method of the present invention, the protective insulating film formed may be etched back before formation of the insulating film by HDP-CVD.
If the opening between the interconnections is blocked off by the protective insulating film, it is possible to etch back the protective insulating film to reopen the opening. Accordingly, the insulating film can be formed by HDP-CVD to successfully fill in the gap between the interconnections to the bottom. Of course, sputtering by HDP-CVD can accompany this etch back.
The step of forming the interconnections in the method of the present invention may include the step of forming a layer to be under protective layers located under the interconnections.
With this configuration, even if the interconnection is made of aluminum, for example, tolerance to stress migration and electric migration can be improved.
In the method of the present invention, the interconnection may be an aluminum interconnection.
With this configuration, it is possible to u
Kamiura Yuuki
Kawata Hiroyuki
Oda Kouji
Sawada Mahito
Shibata Kouji
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nhu David
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