Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-28
2003-06-17
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S308000, C257S307000
Reexamination Certificate
active
06580113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a storage node and to a manufacturing method of such a semiconductor device.
2. Description of the Background Art
FIG. 24
is a cross-sectional view showing a former semiconductor device
10
.
FIG. 25
is a top perspective view showing the structure of the semiconductor device
10
.
As shown in
FIG. 24
, the semiconductor device
10
comprises a plurality of bit lines
12
. The bit lines
12
are covered with a tetra-ethyl-ortho-silicate (TEOS) film
14
, which is covered with a SiN film
16
.
The semiconductor device
10
is also provided with a plurality of storage node contacts (hereinafter abbreviated as “SC”)
18
each of which penetrates through the TEOS film
14
and the SiN film
16
, and a plurality of storage nodes
20
each of which is in contact with the SC
18
and is provided on the TEOS film
14
. The SC
18
and the storage node
20
are formed from doped polysilicon. A cell plate and an electrode layer (neither of which is shown in
FIG. 24
) are formed on the storage node
20
from a dielectric material and a conductive material, respectively. Together with the cell plate and the electrode layer, the storage node
20
acts as a capacitor for storing electric charge.
In
FIG. 25
, the semiconductor device
10
is described so that the bit lines
12
extend in a lateral direction. As shown in
FIG. 25
, a plurality of active regions
22
separated from one another by an isolation oxide film are formed on the silicon substrate of the semiconductor device
10
. A plurality of transfer gates
24
are formed on the active regions
22
so as to extend perpendicular to the bit lines
12
. On both sides of each of the transfer gates
24
are provided wiring frames
26
formed from a silicon oxide film. The transfer gates
24
and the bit lines
12
are insulated from each other by an interlayer film which is provided between thereof.
The area of the active region
22
that is positioned beneath the transfer gate
24
acts as a channel region of a transistor, and the areas of the active region
22
that are positioned on opposite sides of the channel region act as the source/drain regions of the transistor. Each of the source/drain regions is connected to a storage node
20
or a bit line
12
by way of the SC
18
or a bit line contact (hereinafter abbreviated as “BC”)
In the former semiconductor device
10
, the SC
18
must not interfere with or form a short circuit with the bit line
12
. Further, in the former semiconductor device
10
, the SC
18
must be formed so as to penetrate through a plurality of layers interposed between the active region
22
and the storage node
20
of the silicon substrate, i.e., a plurality of interlayer films containing the transfer gate
24
and the bit line
12
. To form DRAM of the order of 64 megabits into the aforementioned structure, the SC
18
must be formed so as to assume a diameter of about 0.1 &mgr;m and a length of about 1 &mgr;m.
In order to form the SC
18
to a diameter of about 0.1 &mgr;m during the process of manufacturing the semiconductor device
10
, photolithography for opening a contact hole for use as the SC
18
must be carried out through use of a high-precision manufacturing apparatus, i.e., a stepper which enables high-precision positioning. Further, forming such a contact hole requires a halftone mask which enables high-precision photolithography, as well as a processing for diminishing the diameter of the contact hole after opening thereof. For these reasons, inexpensive manufacture of high-integration DRAM based on the former DRAM structure has been difficult.
In the semiconductor device
10
, contact resistance between the SC
18
and the active region
22
and contact resistance between the SC
18
and the storage node
20
become greater as the diameter of the SC
18
becomes narrower. In a DRAM structure in which the SC
18
is ensured of assuming only a diameter of about 0.1 &mgr;m, great electrical resistance is likely to arise between the storage node
20
and the active region
22
. Therefore, by employing the former DRAM structure, it is difficult to realize a high-integration and power-efficient DRAM.
In the semiconductor device
10
, in order to impart an enough capacity to each memory cell, it is necessary to ensure a sufficient surface area on the storage node
20
. In the former structure, the surface area of the storage node
20
can be increased by increasing the height of the storage node
20
. However, the higher the storage node
20
, the more likely the storage node
20
is to fall. For this reason, when the former DRAM structure is employed, it is difficult to manufacture a high-integration DRAM at high-yield.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the previously-mentioned problems, and a general object of the present invention is to provide a novel and useful semiconductor device and a manufacturing method thereof.
A more specific object of the present invention is to provide a high-integration, highly-power-efficient semiconductor device which can be inexpensively manufactured at high yield.
The above object of the present invention is achieved by a semiconductor device described below. The semiconductor device includes a plurality of first wiring patterns formed on a silicon substrate. The first wiring patterns are covered with an interlayer film. On the interlayer film is provided a hollow node formed from conductive material. The semiconductor device also includes a contact hole which penetrates through the interlayer film without exposing the first wiring patterns and which exposes the surface of the silicon substrate within the hollow node. The interior surface of the hollow node, the interior surface of the contact hole, and the exposed portion of the silicon substrate are covered with a conductive layer.
A second object of the present invention is to provide a method of inexpensively manufacturing a high-integration, highly-power-efficient semiconductor device at high yield.
The above object of the present invention is achieved by a method of manufacturing a semiconductor device described below. The method includes the steps of forming a plurality of wiring patterns on a silicon substrate; forming an interlayer film so as to cover the first wiring patterns; depositing conductive material on the interlayer film; forming the interior surface of the hollow node by etching the conductive material; forming a contact hole in the hollow node so as to expose the surface of the silicon substrate, by etching the interlayer film so as not to expose the first wiring patterns; forming a conductive layer so as to cover the interior surface of the contact hole to a predetermined thickness, in the region ranging from the interior surface of the hollow node to the exposed portion of the silicon substrate; and forming the exterior surface of the hollow node by etching the conductive material.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5110752 (1992-05-01), Lu
patent: 5278091 (1994-01-01), Fazan et al.
patent: 5315140 (1994-05-01), Sugahara et al.
patent: 5323343 (1994-06-01), Ogoh et al.
patent: 5352913 (1994-10-01), Chung et al.
patent: 5381365 (1995-01-01), Ajika et al.
patent: 5406102 (1995-04-01), Oashi
patent: 5447878 (1995-09-01), Park et al.
patent: 5449636 (1995-09-01), Park et al.
patent: 5608241 (1997-03-01), Shibuya et al.
patent: 5612558 (1997-03-01), Harshfield
patent: 5629223 (1997-05-01), Thakur
patent: 5696014 (1997-12-01), Figura
patent: 5726459 (1998-03-01), Hsu et al.
patent: 5920124 (1999-07-01), Kimura
patent: 6054385 (2000-04-01), Gardner et al.
patent: 6078492 (2000-06-01), Huang et al.
patent: 6160285 (2000-12-01), Schugraf et al.
pate
Watanabe Shinya
Yasumura Shunji
Loke Steven
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Owens Douglas W.
LandOfFree
Semiconductor device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3135355