Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-07
2003-07-15
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S392000
Reexamination Certificate
active
06593611
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having semiconductor memory provided with a capacitor, as well as a method of manufacturing the semiconductor device.
2. Description of the Background Art
In recent years, in association with an increase in the degree of integration of a semiconductor integrated circuit, miniaturization of a semiconductor element has been pursued and realized rapidly. Particularly, miniaturization of a capacitor formed in DRAM (Dynamic Random Access Memory), which is one type of semiconductor memory device requiring a high degree of integration, directly results in a decrease in the storage capacity of the DRAM. Thus, miniaturization of the capacitor inevitably involves determining the way in which the desired capacity of the capacitor is to be ensured.
In an effort to solve such a problem, an attempt has been made to form a capacitor into a three-dimensional structure. Specifically, an electrode is formed into a three-dimensional structure in order to enlarge the surface area of electrodes of a capacitor; for example, three-dimensional capacitors that have been developed include a thick-film-type capacitor whose electrodes are thick, a fin-type capacitor comprising a stack of fin-shaped electrodes, and a cylindrical capacitor whose electrodes are formed cylindrically.
Aside from these three-dimensional capacitors, there is also proposed in; e.g., Applied Physics Vol. 61, No. 11, pg. 1147 (1992), a method of increasing the surface area of electrodes by forming minute irregularities on the surface thereof.
FIG. 20
is a cross-sectional view showing a conventional semiconductor memory device whose storage node electrodes are cylindrical and in which minute irregularities are formed in the surface of the electrode.
The structure of the semiconductor memory device will now be described.
Referring with
FIG. 20
, an element isolation oxide film
102
for isolating an element region is formed on the primary surface of a silicon substrate
101
. On the element region isolated by the element isolation oxide film
102
is formed gate electrodes
103
a
and
103
b
by way of a gate oxide film (not shown) of the silicon substrate
101
. N-type impurity diffusion layers
104
a
and
104
b
are formed so as to sandwich the gate electrode
103
a
for acting as source or drain region. The n-type impurity layers
104
a
and
104
b
constitute a transistor element
150
together with the gate electrode
103
a.
On the silicon substrate
101
and the transistor element
150
is formed a insulating film
105
which has an opening
106
extending to the surface of the n-type impurity diffusion layer
104
b
. The inside of the opening
106
is filled with polysilicon, thus constituting a plug layer
107
. An interlayer insulating film
108
is formed on the plug layer
107
and the insulating film
105
so as to have a cylindrical opening
109
extending to the surface of the plug layer
107
. A capacitor
200
is fabricated to cover the inside of the cylindrical opening
109
and the certain region of the interlayer insulating film
108
.
The capacitor
200
has minute irregularities
111
on the surface thereof, and comprises a cylindrical storage node
110
formed within the cylindrical opening
109
and is electrically connected to the plug layer
107
; a capacitor insulating film
112
formed on the surface of the cylindrical storage node electrode
110
, as well as on the surface of the interlayer insulating film
108
; and a cell plate electrode
113
formed on the capacitor insulating film
112
as an upper electrode.
A method of forming the semiconductor memory device shown in
FIG. 20
will now be described.
First, the element isolation oxide film
102
, the transistor element
150
, the insulating film
105
, and the plug layer
107
filling the opening
106
are formed in accordance with known manufacturing methods.
Then, the interlayer insulating film
108
is formed on the plug layer
107
and the insulating film
105
. The cylindrical opening
109
is selectively opened through use of photolithography so as to communicate with the opening
106
.
Next, the cylindrical storage node electrode
110
has been formed within the cylindrical opening
109
from an amorphous silicon film doped with n-type impurities. The surface of the cylindrical storage node
110
is subjected to heat treatment, thus forming the minute irregularities
111
.
A nitride-oxide film and a polysilicon film doped with an n-type impurity are sequentially deposited on the cylindrical storage node electrode
110
. On the polysilicon film is formed a resist pattern so as to have a desired pattern. The polysilicon film and the nitride-oxide film are etched in sequence while the resist pattern is used as a mask, thus forming the capacitor insulating film
112
and the cell plate electrode
113
. Since the thickness of the surface of the capacitor insulating film
112
is usually very thin, the irregularities
111
formed on the surface of the storage node electrode
110
are reflected on the surface of the film
112
, exactly as they are.
The cell plate electrode
113
is formed by the low-pressure CVD technique of tube type while using raw material gas containing n-type impurities such as phosphorous.
Finally, desired heat treatment is performed for activation the n-type impurities contained in the cylindrical storage node electrode
110
and the cell plate electrode
113
.
In the semiconductor memory device manufactured in the manner as mentioned above, the storage node electrode
110
is formed into a cylindrical shape, and the minute irregularities
111
are formed on the surface of the storage node electrode
110
. Accordingly, desired capacitance can be ensured without involvement of an increase in the planar area occupied by the capacitor
200
.
However, the conventional semiconductor memory device has problems that would described below.
FIG. 21
is an enlarged and exaggerated cross-sectional view showing the adhesion state between the irregular surface of the capacitor insulating film
112
formed on the cylindrical storage node electrode
110
and the surface of the cell plate electrode
113
formed on the capacitor insulating film
112
.
As shown in
FIG. 21
, the conventional cell plate electrode
113
cannot sufficiently reflect the irregularities
111
a
and
111
b
formed on the surface of the capacitor insulating film
112
. Consequently, the effect of increasing the surface area by virtue of irregularities cannot be sufficiently reflected in the semiconductor memory device, thus resulting in a failure to ensure desired capacity.
Further, if the aspect ratio (height/diameter)of the cylindrical section of the cylindrical storage node electrode
110
becomes greater in association with an increase in the degree of miniaturization of the semiconductor device in question, the coverage becomes degraded with regard to the cylindrical storage node electrode
110
. Thus, as shown in
FIG. 20
, the interior walls of the cell plate electrode
113
come into contact with each other at the top portions thereof, to thereby constitute a cavity
114
and impair the electrical characteristics or reliability of the semiconductor device.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the foregoing problems in the background art.
A first object of the present invention is to provide a method of manufacturing a semiconductor device, wherein a cell plate electrode is formed so as to reliably cover minute irregularities formed on the surface of a cylindrical storage node electrode.
A second object of the present invention is to provide a method of manufacturing a semiconductor device, wherein a cell plate is formed so as to reliably cover a cylindrical storage node electrode having a high aspect ratio.
A third object of the present invention is to provide a method of manufacturing a semiconductor device, wherein a cell pla
Inaba Yutaka
Mori Kiyoshi
Ogata Tamotu
Tsuchimoto Junichi
Lee Calvin
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Smith Matthew
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