Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-09-07
2003-04-08
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C438S622000, C257S774000
Reexamination Certificate
active
06545360
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device having a memory cell portion and manufacturing method thereof, and more particularly, to a semiconductor device directed to lowering of the resistance of the connection portion of a field effect transistor and a manufacturing method thereof.
2. Description of the Related Art
Semiconductor devices using a MOS (Metal Oxide Semiconductor) field effect transistor have been developed in various fields and implemented as a device having multiple functions as the technique of reducing the size and the technique of high density integration have advanced. As a typical semiconductor device having multiple functions, a semiconductor device including both a DRAM (Dynamic Random Access Memory) and a logic is known. Disadvantages associated with the multiple function semiconductor device will be now described.
FIGS. 1A and 1B
are cross sectional views showing the memory cell portion and peripheral circuit portion of a conventional DRAM. As shown in
FIGS. 1A and 1B
, in the peripheral circuit portion, a MOS transistor having an n type diffusion layer and a p type diffusion layer is formed. As shown in
FIG. 1A
, a p well
242
is formed on the surface of a semiconductor substrate
241
, and a plurality of element isolation oxide films
243
are formed on the surface of the p well
242
. Thus, a memory cell portion
260
and a peripheral circuit portion
270
are partitioned and there are a plurality of element regions in the memory cell portion
260
and the peripheral circuit portion
270
. At the surface of the p Well
242
in an element region in the memory cell portion
260
, an n type diffusion layer
244
is formed. At the surface of the p well
242
in an element region in the peripheral circuit portion
270
, an n type diffusion layer
274
is formed. The n type diffusion layer
274
in the peripheral circuit portion
270
is formed to a position deeper than the n type diffusion layer
244
in the memory cell portion
260
. An interlayer insulating film
246
is formed at the upper surfaces of these element regions. In the interlayer insulating film
246
, there is a memory cell portion contact
247
connected to the n type diffusion layer
244
and filled with a phosphorus-doped polysilicon plug
250
formed of a phosphorus-doped polysilicon film. Also in the interlayer insulating film
246
, there is a peripheral circuit portion contact
248
connected to the n type diffusion layer
274
in the peripheral circuit portion
270
, and a phosphorus-doped polysilicon plug
251
formed in the same process is filled therein. A metal interconnection
255
connected to these phosphorus-doped polysilicon plugs
250
and
251
is also formed.
In
FIG. 1B
, a p type diffusion layer
245
is formed on the surface of the p well
242
in the peripheral circuit portion
270
. An interlayer insulating film
266
is formed on the interlayer insulating film
246
and the metal interconnection
255
. A peripheral circuit portion contact
258
reaching the p type diffusion layer
245
is formed in the interlayer insulating films
266
and
246
, and a metal plug
254
is filled therein. A metal plug
256
connected to the metal interconnection
255
is formed in the interlayer insulating film
266
. Similarly to
FIG. 1A
, in the memory cell portion
260
, a phosphorus-doped polysilicon plug
250
is filled in the memory cell contact portion
247
provided in the interlayer insulating film
246
, and is connected to the n type diffusion layer
244
.
The phosphorus-doped polysilicon plug
250
normally has the same conductivity type as that of the n type diffusion layer
244
. As a result, when an n type polysilicon plug of the same conductivity type as the polysilicon plug in the memory cell portion
260
is formed in the peripheral circuit portion contact
258
on the p type diffusion layer
245
in the peripheral circuit portion
270
, a pn junction forms and application of a voltage across the region between the n type polysilicon plug and the p type diffusion layer causes an undesirable rectifying effect therebetween. Therefore, an n type polysilicon plug cannot be used for the peripheral circuit portion contact
258
, and a metal plug is used instead. Thus, the p type diffusion layer
245
in the peripheral circuit portion is connected to the upper metal film interconnection
265
through the metal plug
254
filling the peripheral circuit portion contact
258
and then connected to the metal interconnection
255
through the metal plug
256
provided in the interlayer insulating film
266
.
Note however that as the size of a memory cell portion contact is reduced with reduction in the size of elements, the resistance of the n type polysilicon plug increases, which could cause a fault in the operation of cells. A metal plug may be used instead of the n type polysilicon plug for the contact of the memory cell portion, but the use of the metal plug increases diffusion layer leakage. As a result, a metal plug cannot be used for forming the memory cell portion contact unlike for the peripheral circuit portion contact.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a multifunction semiconductor device including memory cells with a reduced size, having a low resistance contact plug without diffusion layer leakage in the memory cell portion and a low resistance contact plug in the peripheral circuit portion of the memory cell portion.
A semiconductor device according to a first aspect of the present invention includes: semiconductor substrate; an element formed on said substrate; an interlayer insulating film formed on said semiconductor substrate; a first opening provided in said interlayer insulating film and reaching the surface of said semiconductor substrate; a second opening having a larger opening size than the first opening; a first plug having a lower conductive silicon film filled within a lower portion of said first opening and a metal film filled within an upper portion of said first opening; and a conductive, second plug filled within said second opening.
A semiconductor device according to a second aspect of the present invention includes: a semiconductor substrate; an element formed on said substrate; a gate insulating film formed on said semiconductor substrate; first and second gate electrodes formed on said gate insulating film; a sidewall insulating film formed on a sidewall of said gate electrode; an interlayer insulating film covering an upper surface of said semiconductor substrate including said gate electrode and said sidewall insulating film; first and second openings provided in said interlayer insulating film and reaching the surface of said semiconductor substrate; and conductive, first and second plugs filled within said first and second openings, respectively, said first gate electrode being formed at a first interval smaller than twice the thickness of said sidewall insulating film, and said second gate electrode being formed at a second interval larger than twice the thickness of said sidewall insulating film.
In the semiconductor devices according to the first and second aspect of the present invention, the first plug has a conductive silicon film filled within a lower layer portion of the first opening and the plug upper layer metal film filled within an upper layer and the second plug has conductive film filled within the second opening and can be directly connected to a diffusion layer. Therefore, the resistance of second plug reduced. In addition the device will not degrade the leakage characteristic in the first plug formed in a memory cell.
A method of manufacturing the semiconductor device according to a first aspect of the present invention includes the steps of: forming first and second diffusion layers on a surface of a semiconductor substrate; forming an interlayer insulating film on said semiconductor substrate including said first and second diffusion layers; forming first and second openings in a region of the interlaye
Hamada Takehiko
Matsuki Takeo
Ohkubo Hiroaki
Berry Renee′ R
NEC Corporation
Nelms David
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