Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-21
2002-11-12
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000
Reexamination Certificate
active
06479853
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, comprising a self align contact hole.
DESCRIPTION OF THE RELATED ART
The integration degree of a semiconductor device is mainly improved by the progress of the fine processing technology and also depends on the advancement of the multilayer wiring technology. From a viewpoint of the improvement of the integration degree, one of the important technical issues in the multilayer wiring technology is how to connect an upper wiring layer directly to a lower wiring layer avoiding a connection via a middle wiring layer. As a typical example of a solution of such a technical issue, a self align contact hole is now being watched. The self align contact hole reaching from the upper wiring layer to the lower wiring layer is provided at the middle wiring layer as a self matching i.e. at a vacant part of the middle wiring layer, at a lower part than an upper surface of the middle wiring layer. At a part of the self align contact hole, an insulation separation between the third wiring layer (and the first wiring layer) and the second wiring layer is implemented by an insulation film spacer provided at a side of the self align contact hole.
The self align contact hole is adopted in a normal multilayer wiring and is also becoming larger usage in DRAM corresponding to the reduction of the size of memory cell. In particular, at the COB (Capacitor Over Bit-line) structure DRAM provided a storage node electrode at the upper layer of the bit-line, a tendency to use a self align contact hole for a bit contact hole and a node contact hole is getting larger, wherein a bit contact hole is a hole to connect a bit line to one side of a source drain area and a node contact hole is a hole to connect a storage node electrode that is a lower electrode of capacitor to the other side of a source drain area. In this case, the bit contact hole is self matching to a gate electrode which also serves as a word line, the node contact hole is self matching to both a gate electrode and a bit line. Next, the conventional self align contact hole is explained, with an example which the bit contact hole and the node contact hole of the COB structure DRAM are made of the self align contact holes.
Referring to
FIG. 1
showing a plan view of DRAM,
FIGS. 2A and 2B
showing section views of DRAM and section views of both I—I line and, II—II line of FIG.
1
and
FIGS. 3A and 3B
showing section views of DRAM and section views of both III—III line and IV—IV line of
FIG. 1
, the constitution of the COB structure DRAM in which the bit contact hole and the node contact hole are made of self align contact hole are explained in a below description. An elements forming area is shown in hatching in
FIG. 1
, however, the drawing of a capacity insulation film constituting a capacitor and a cell plate electrode are omitted in
FIGS. 1
,
2
A,
2
B,
3
A and
3
B.
On a surface of a P type silicon substrate
301
, T formed element forming areas are disposed regularly, a gate oxide film
303
with about 10 nm thickness is provided on the surface of
301
. On a surface of element separation areas surrounding these element forming areas of the P type silicon substrate
301
, a field oxide film
302
with for example LOCOS type about 300 nm thickness is provided. On the surface of the field oxide film
302
and the gate oxide film
303
, a gate electrode
304
also served as a word line is provided in a certain direction in parallel. A line width and an interval of these gate electrodes
304
are for example about 0.4 &mgr;m respectively, these gate electrodes
304
are constituted of a tungsten polycide film laminated an about 150 nm thickness tungsten silicide film to an about 100 nm thickness N type polycrystal silicon film (not shown in Figs.). On the surface of the P type silicon substrate
301
of the respective element forming areas, the gate electrode
304
, one of N type source drain area
305
self matching to the field oxide film
302
and two N type source drain areas
306
are provided. The minimum line width and the minimum interval of the N type source drain area
305
and
306
are respectively about 0.4 &mgr;m.
The surface of the P type silicon substrate
301
including the gate electrode
304
, the field oxide film
302
and the gate oxide film
303
is covered with an insulation film between layers
310
a
made of a silicon oxide type insulation film. The surface of the insulation film between layers
310
a
is flattened and the film thickness of the insulation film between layers
310
a
from the surface of the P type silicon substrate
301
is about 500 nm. The upper surface of the insulation film between layers
310
a
and the bottom face of the insulation film between layers
310
a
covering directly the gate electrode
304
are constituted of at least a silicon oxide film.
At the insulation film between layers
310
a
, a bit contact hole
311
reaching the N type source drain area
305
penetrating the insulation film between layers
310
a
and the gate oxide film
303
from the surface of this insulation film between layers
310
a
is provided. The bit contact hole
311
is formed in self matching for the gate electrode
304
and penetrates the insulation film between layers
310
a
of the vacant part of the gate electrode
304
. At the upper surface of the insulation film between layers
310
a
, an upper end bore of the bit contact hole
311
is about 0.5 &mgr;m but the minimum bore of the bit contact hole
311
being at the lower part than the upper face of the gate electrode
304
is the same as an interval of the gate electrode
304
and is about 0.4 &mgr;m, this minimum bore is a bore of an orthogonal direction of the gate electrode
304
. The upper face and a part of a side face of the gate electrode
304
are exposed by the bit contact hole
311
. The side face of the bit contact hole
311
is covered directly with a silicon oxide film spacer
312
of about 100 nm thickness except a part of the side face of the exposed gate electrode
304
.
On the surface of the insulation film between layers
310
a
, a bit line
317
connecting to the N type source drain area
305
via the bit contact hole
311
is provided in parallel in an orthogonal direction of the gate electrode
304
. The bit line
317
is the same as the gate electrode
304
, is constituted of the tungsten polycide film laminated a tungsten silicide film
337
with about 150 nm thickness to an N type polycrystal silicon film
336
with about 100 nm thickness. A wiring pitch of the bit line
317
is about 0.8 &mgr;m, a line width and an interval of the bit line
317
at the part of the bit contact hole
311
are about 0.5 &mgr;m and 0.3 &mgr;m, the line width and the interval of the bit line
317
except the part of the bit contact hole
311
is about 0.4 &mgr;m. The surface of the insulation film between layers including these bit line
317
is covered with an insulation film between layers
320
a
constituting of a silicon oxide type insulation film. An upper face of the insulation film between layers
320
a
is also flattened and a thickness of the insulation film between layers
320
a
from the surface of the insulation film between layers
310
a
is about 350 nm. The upper face of the insulation film between layers
320
a
and the bottom face of the insulation film between layers
320
a
covering directly the bit line
317
are at least formed by the silicon oxide film (
FIGS. 1
,
2
A and
2
B).
In the insulation film between layers
320
a
, a node contact hole
321
reaching an N type source drain area
306
penetrating these insulation film between layers
320
a
,
310
a
and the gate oxide film
303
from this surface is provided. A node contact hole
321
is formed in self matching for the bit line
317
and penetrates the insulation film between layers
320
a
of the vacant part of the bit line
317
, further is formed in self matching for the gate electrode
304
and penetrates the insulation film between
NEC Corporation
Nguyen Cuong Q
Sughrue & Mion, PLLC
Thomas Tom
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