Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1995-06-02
2002-12-24
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S391000, C257S404000
Reexamination Certificate
active
06498376
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a construction of a channel region of an insulating gate field effect transistor (hereinafter referred to as a MISFET) constituting a semiconductor device of an integrated circuit and more particularly to a semiconductor device in which a surface inversion voltage (threshold voltage) of the channel region which is determined by impurity concentrations and thicknesses of a gate insulating film of the channel region is controlled.
The present invention relates to a semiconductor device of an integrated circuit composed of MISFETs having a plurality of threshold voltages formed on the same substrate and to a manufacturing method thereof.
The present invention also relates to a semiconductor device of an integrated circuit having different conductive MISFETs on the same substrate and to a manufacturing method thereof.
The present invention further relates to a semiconductor device of an integrated circuit having high withstand voltage and low voltage MISFETs to which different gate voltages are applied on the same substrate and to a manufacturing method thereof.
The present invention furthermore relates to a semiconductor device comprising an analog circuit formed and a digital circuit on the same substrate and to a manufacturing method thereof.
The present invention relates additionaly to a semiconductor device formed on a thin film semiconductor provided on an insulating layer and to a manufacturing method thereof.
FIGS. 38A through 38C
are schematic plan views representing MISFETs within a prior art semiconductor device of an integrated circuit.
Note that the explanation of the present specification is made exemplifying a MOSFET in which an insulating layer interposed between a metal gate electrode and a semiconductor substrate is a silicon oxide film, as a typical example of the MISFET.
FIGS. 38A
to
38
C schematically show a source, drain and gate of three kinds of transistors, and aluminum metallic wirings and other elements are omitted to simplify the description.
Transistors
1
,
2
and
3
have each different threshold voltage (V
TH
).
FIG. 39
is a schematic section view illustrating the MOSFET within the prior art semiconductor integrated circuit.
In the transistor
1
, an impurity concentration of a channel region
4004
is set at a value of an impurity concentration of a semiconductor substrate
4006
and a threshold voltage determined by the impurity concentration of the channel region
4004
and a thickness of a gate insulating film
4005
is denoted as V
TH1
.
When it is desired to differentiate a threshold voltage V
TH2
Of the second transistor
2
from V
TH1
, a channel region
2
having an impurity concentration which is different from that of the channel region
1
of the transistor
1
is formed by optically patterning a photoresist by using a glass mask and others for selecting a region to which an impurity is doped (photolithographic technique) and by doping the impurity via the gate insulating film
4005
by ion implantation and others using the photoresist selectively formed as a mask.
At this time, a pattern
3905
of the glass mask
1
for ion implantation for selecting the region to which the impurity is doped is created so as to be slightly larger than the channel region to cover the whole surface thereof considering a dislocation of registration of the glass mask as shown in FIG.
38
B and the photoresist is removed slightly more than the channel region to dope the impurity to the channel at the region where the photoresist is removed.
The gate insulating film
4005
is normally formed of a silicon oxide film having a homogeneous thickness from around 10 nm to 100 nm.
By constructing as described above, the transistor
2
having V
TH2
which is different from V
TH1
of the transistor
1
may be formed. In the same manner, a transistor having a necessary threshold voltage may be formed by doping a necessary impurity like V
TH3
of the transistor
3
.
Further, although not shown in the figure, in a semiconductor device of an integrated circuit in which a high voltage MOSFET having a thick gate oxide film and a low voltage MOSFET having a thin gate oxide film are provided on the surface of the same substrate, a concentration of a homogeneous impurity region of channel region of each MOSFET is controlled by a photolithographic technique in order to equalize each threshold voltage to almost the same value.
Similarly, in a CMOS type integrated circuit comprising P-type and N-type MOSFETs, threshold voltages are equalized to almost the same value by separate impurity doping processes.
SUMMARY OF THE INVENTION
However, because the MOSFETs within the prior art semiconductor device of the integrated circuit have the channel region having the homogeneous impurity concentration and the gate insulating film having the uniform thickness as described above, the surface inversion voltage of the channel becomes constant and hence processes for doping a necessary number of types of impurities or impurity concentrations to the channel region have been necessary in order to form transistors having a plurality of types of threshold voltages within the semiconductor device of the integrated circuit formed on a single semiconductor substrate.
Accordingly, it has been costly and been a restriction in designing the circuit to form the transistors having the plurality of types of threshold voltages within the semiconductor device of the integrated circuit formed on single semiconductor substrate.
Further, a plural number of photolithographic processes have been necessary to adjust the threshold voltages matching with the range of the power supply voltage in the semiconductor device of the integrated circuit in which transistors having a structure in which threshold voltages differ before an impurity is doped to the channel region are provided on the same substrate. Accordingly, a manufacturing period has been prolonged and a manufacturing cost has been increased to manufacture the semiconductor device in which the threshold voltages of the MOSFETs having different gate insulating films, different substrate concentrations or different conductive types are controlled.
In order to solve the aforementioned problems, the present invention adopts the following means.
As first means, channel regions having different surface inversion voltages such that the channel surface is inverted by more than two different gate voltages are provided within the same channel of a MOSFET.
Further, plural types of ratios of plane areas of a first surface inversion voltage area and a second surface inversion voltage region or plural types of individual plane size or shape of the first surface inversion voltage region and the second surface inversion voltage region are provided.
As second means, the second surface inversion voltage region is divided into a plurality of plane shapes.
There are the following methods as examples of the method of dividing the region into the plurality of plane shapes:
1) divide in strips parallel to the direction of the channel length;
2) divide in strips parallel to the direction of the channel width;
3) divide in dots; and
4) divide in checker pattern.
As third means, the channel region having more than two different surface inversion voltages is obtained by forming regions having more than two different impurity concentrations (channel impurity region) on the surface of the same channel region of the MOSFET.
As fourth means, the channel impurity region described in the third means is formed to be shallower than a depth of junction of the source and drain regions.
As fifth means, a first MOSFET and a second MOSFET each having a gate insulating film formed with different thicknesses are formed and the first through fourth means described above are applied to each of them.
As sixth means, a first MOSFET is formed on a first conductive semiconductor substrate and a second MOSFET is formed within a well region having a different impurity concentration from that of the semiconductor substrate but formed in the
Kaneko Tetsuya
Kojima Yoshikazu
Konishi Haruo
Kubo Kazuaki
Machida Toru
Adams & Wilks
Cao Phat X.
Seiko Instruments INC
Weiss Howard
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