Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-30
2002-07-30
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S273000, C257S370000
Reexamination Certificate
active
06426533
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuit having an N channel MOS (Metal Oxide Semiconductor) field effect transistor, a P channel MOS field effect transistor and a bipolar transistor, and a method of manufacturing the same.
2. Description of the Background Art
Conventionally, a BiCMOS circuit has been used as a circuit of semiconductor device, which includes therein a bipolar transistor with large output allowing high-speed operation and a CMOS (Complementary Metal Oxide Semiconductor) transistor with low power dissipation performance allowing high-level integration.
Hereinafter, a structure of a conventional BiCMOS circuit and a manufacturing method thereof will be described with reference to
FIGS. 34
to
43
. In a conventional method of manufacturing a BiCMOS circuit, a p type underside isolating layer
105
, an n type collector buried layer
102
of relatively high concentration, an n type buried layer
103
, and a p type buried layer
104
are formed, spaced apart from one another by prescribed distances, substantially at the same depth from the surface of a p type semiconductor substrate
101
.
Next, an n type epitaxial layer
106
of relatively low concentration is formed by epitaxial growth in a region from the surface of semiconductor substrate
101
to reach collector buried layer
102
, that is to be an active region of a bipolar transistor. Adjacent to n type epitaxial layer
106
, an n type collector wall region
108
of relatively high concentration is formed from the surface of semiconductor substrate
101
to collector buried layer
102
. In an active region of a P channel MOS (p type Metal Oxide Semiconductor) transistor, an n type well
109
of relatively low concentration is formed from the surface of semiconductor substrate
101
reaching collector buried layer
103
.
In an active region of an N channel MOS (n type Metal Oxide Semiconductor) transistor, a p type well
110
of relatively low concentration is formed from the surface of semiconductor substrate
101
to reach p type buried layer
104
of relatively high concentration. A p type isolating region
111
of low concentration is formed from the surface of semiconductor substrate
101
reaching a respective underside isolating layer
105
.
Next, isolating oxide films
107
e
and
107
g
are formed on the respective surfaces of isolating regions
111
to separately form element forming regions. An isolating oxide film
107
f
for separating collector wall region
108
from n type epitaxial layer
106
, an isolating oxide film
107
h
for separating n type well
109
from p type well
110
, and an isolating oxide film
107
i
for separating p type well
110
from another region are also formed. Thereafter, on n type epitaxial layer
106
, collector wall region
108
, n type well
109
, and p type well
110
, which are to be active regions, oxide films
107
b
,
107
a
,
107
c
, and
107
d
are formed, respectively, which results in a structure as shown in FIG.
34
.
Next, an n type polycrystalline silicon (polysilicon) film doped with phosphorus is deposited on the entire surface of the structure in
FIG. 34
, with a film thickness of 1500 Å. Thereafter, a tungsten silicide film with a film thickness of 2000 Å is formed on the polysilicon film. Next, the tungsten silicide film, the polysilicon film, oxide films
107
a
and
107
b
, and oxide films
107
c
and
107
d
are selectively etched to form, on the surface of n type well
109
, a gate electrode
113
consisting of a polysilicon film
113
a
and a tungsten silicide film
113
b
and a gate oxide film
112
, and to form, on the surface of p type well
110
, a gate electrode
115
consisting of a polysilicon film
115
a
and a tungsten silicide film
115
b
and a gate oxide film
114
. A structure shown in
FIG. 35
is thus obtained.
Thereafter, as shown in
FIG. 36
, a mask
116
is formed to expose p type well
110
. An n type impurity
200
, e.g., high concentration phosphorus (hereinafter referred to as “P”) ions, is then introduced at implant energy of 70 KeV with a dosage of 2×10
13
cm
−2
, thereby forming n type source/drain regions
117
a
and
117
b
in p type well
110
, as shown in FIG.
37
. Thereafter, mask
116
is removed and an oxide film is deposited on the entire surface. Etching is then conducted to form sidewall oxide films
119
a
,
119
b
and sidewall oxide films
118
a
,
118
b
on respective sides of gate electrodes
113
and
115
. Thereafter, as shown in
FIG. 37
, a mask
120
is formed to expose the surface of p type well
110
, and an n type impurity
300
, e.g., high concentration arsenic (hereinafter referred to as “As”) ions, is introduced at implant energy of 50 KeV with a dosage of 4×10
15
cm
−2
. Accordingly, n type source/drain regions
120
a
and
120
b
with an LDD (Lightly Doped Drain) structure are formed in p type well
110
, as shown in FIG.
38
.
Next, as shown in
FIG. 38
, masks
121
a
and
121
b
are formed to expose n type well
109
. Thereafter, a p type impurity
400
of high concentration, e.g., boron fluoride (hereinafter referred to as “BF
2
”) ions, is introduced into n type well
109
at implant energy of 40 KeV with a dosage of 4×10
15
cm
−2
, as shown in FIG.
38
. Accordingly, p type source/drain regions
122
a
and
122
b
, as shown in
FIG. 39
, are formed.
Next, a 2000 Å thick polysilicon film is deposited on the entire surface, and BF
2
ions, for example, are introduced at implant energy of 40 KeV with a dosage of 4×10
15
cm
−2
to form a conductive polysilicon film that is to be a base electrode. In the step of implanting BF
2
ions, the BF
2
ions that have been transmitted through the polysilicon film are introduced into n type epitaxial layer
106
, thereby forming a portion that is to be a p type external base region. Thereafter, a CVD oxide film with a film thickness of 3000 Å is further deposited to cover the entire surface. The CVD oxide film, the polysilicon film and the upper portion of n type epitaxial layer
106
are then dry etched using a mask, thus opening, as shown in
FIG. 39
, a region
106
a
in which an emitter electrode of the bipolar transistor is to be formed. CVD oxide films
123
a
and
124
a
, base electrodes
123
b
and
124
b
made of polysilicon film, and p type external base regions
126
a
and
126
b
are thus formed.
Thereafter, as shown in
FIG. 40
, a p type impurity
500
of high concentration, e.g., BF
2
ion, is introduced at implant energy of 30 KeV with a dosage of 6×10
13
cm
−2
from the emitter opening region into n type epitaxial layer
106
, thereby forming a p type intrinsic base region
128
, as shown in FIG.
41
. Thereafter, a CVD oxide film is formed on the entire surface, and, by framing etching, sidewall oxide films
127
a
,
127
b
,
127
c
, and
127
d
are formed on respective sides of base electrodes
123
b
and
124
b
made of polysilicon film, and of CVD oxide films
123
a
and
124
a
. Next, a polysilicon film doped with no impurities is formed on the entire surface with a film thickness of 2000 Å, a high concentration n type impurity, e.g., As ions, is introduced at implant energy of 50 KeV with a dosage of 1×10
16
cm
−2
therein, and then the film is formed into a shape as shown in
FIG. 42
, which becomes an n type emitter electrode
129
. Here, instead of implanting n type impurity ions, a polysilicon film doped with an n type impurity in advance may be formed.
Next, an interlayer oxide film
130
is formed on the entire surface of the structure shown in FIG.
42
. In interlayer oxide film
130
, contact holes
130
a
,
130
b
,
130
c
,
130
d
,
130
e
,
130
f
and
130
g
are formed to connect to collector wall region
108
, emitter electrode
129
, base electrode
124
a
, p type source/drain r
Igarashi Takayuki
Ohtsu Yoshitaka
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