Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-03-02
2002-03-05
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S783000, C257S685000, C257S686000
Reexamination Certificate
active
06353263
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly concerns a manufacturing method and a structure of a semiconductor device which is allowed to have a high density by stacking a plurality of semiconductor chips.
BACKGROUND OF THE INVENTION
In recent years, along with the miniaturization of semiconductor devices, semiconductor devices which are miniaturized virtually to a chip size have been developed. This miniaturized structure of the semiconductor device is referred to as the CSP (Chip Size Package) structure.
FIGS.
10
(
a
) and
10
(
b
) show examples of semiconductors having the CSP structure.
In the semiconductor device of the CSP structure as shown in FIG.
10
(
a
), a semiconductor chip
50
is installed on a circuit substrate with its surface (hereinafter, referred to as “active face”) having elements (not shown) such as transistors formed thereon facing up (face-up bonding). Electrodes, formed on the active face (hereinafter, referred to as plane electrodes
68
so as to distinguish them from protrusion electrodes), are connected to the circuit substrate
53
by using wires
58
, that is, more specifically, to plane electrodes (not shown) of a wiring layer
54
formed on the circuit substrate
53
. The connection between electrodes using the wires
58
of this type is generally referred to as wire bonding.
Here, in the Figures, reference numeral
60
represents an external terminal that is connected to the wiring layer
54
through a penetration hole
61
formed in the circuit substrate
53
. The surface of the circuit substrate
53
on the side having the installed semiconductor chip
50
, etc. is covered with coat resin
59
.
In a semiconductor device of the CSP structure as shown in FIG.
10
(
b
), the semiconductor chip
50
is packaged on the circuit substrate
53
with its active face facing down (facedown bonding). Protrusion electrodes
56
are formed on plane electrodes (not shown) formed on the active face so that the protrusion electrodes
56
are directly connected to plane electrodes (not shown) on the wiring layer
54
. The connection of this type directly connecting electrodes is generally referred to as flip-chip bonding.
Moreover, in some constructions to be packaged on a portable information apparatus, etc., in an attempt to give “added value” and to further increase the capacity, a plurality of semiconductor chips are included in one package so as to increase the packaging density. In this case, in a multi-chip module in which a plurality of chips are simply placed two-dimensionally, it is not possible to form a semiconductor package that is smaller than the total area of the semiconductor chips.
In this attempt, a technique for further increasing the packaging density by installing a plurality of semiconductor chips in a laminated manner has been proposed. FIGS.
11
(
a
) and
11
(
b
) show such semiconductor devices of the CSP structure having laminated semiconductor chips.
In the semiconductor device of the CSP structure shown in FIG.
11
(
a
), the first semiconductor chip
51
and the second semiconductor ship
52
are installed on a circuit substrate
53
in a laminated manner, and these are respectively connected to the circuit substrate
53
by means of wire bonding by means of wires
58
(Prior Art (1)).
In the semiconductor device of the CSP structure shown in FIG.
11
(
b
), of the first semiconductor chip
51
and the second semiconductor chip
52
laminated on the circuit substrate
53
, the upper second semiconductor chip
52
is connected to the circuit substrate
53
by means of wire bonding, and the lower first semiconductor chip
51
is connected thereto by means of flip-chip bonding (see Japanese Laid-Open Patent Application No. 47998/1993 (Tokukaihei 5-47998) (published on Feb. 26, 1993) and Japanese Laid-Open Patent Application No. 326710/1995 (Tokukaihei 7-326710) (published on Dec. 12, 1995: Prior Art (2)).
Moreover, as illustrated in
FIG. 12
, Japanese Laid-Open Patent Application No. 84128/1988 (Tokukaishou 63-84128) (published on Apr. 14, 1988) discloses a semiconductor device in which a connection system combining the wire bonding and flip-flop chip bonding is adopted in the same manner as Prior Art (2) and in which the upper second semiconductor chip
52
is set to be larger than the lower first semiconductor chip
51
, and these chips are packaged on a circuit substrate
53
′ such as a mother board (Prior Art (3)).
However, in these conventional structures, the size and combination of applicable semiconductor chips are limited, resulting in a problem of limited application.
Specifically, in Prior Art (1) shown in FIG.
11
(
a
), in the case when the upper second semiconductor chip
52
is as large as, or larger than the lower first semiconductor chip
51
, it is not possible to secure a space used for installing plane electrodes
68
a
on the active face of the first semiconductor chip
51
. Therefore, it is not possible to use the second semiconductor chip
52
that is larger than the first semiconductor chip
51
.
In the prior art (2) shown in FIG.
11
(
b
), on the other hand, since the lower first semiconductor chip
51
is connected to the circuit substrate
53
by means of flip-chip bonding, the problem as explained in Prior Art (1) is not raised.
However, in Prior Art (2), the second conductor chip
52
is normally set to be smaller than, or as large as the first conductor chip
51
. This is because when the upper second semiconductor chip
52
is made larger, it is not possible to carry out a stable wire bonding thereon. In other words, since no support exists below the plane electrodes
68
to which wires
58
of the second semiconductor chip
52
are connected, the second semiconductor chip
52
might be damaged due to an impact and a load at the time of wire bonding, or a sufficient load and ultrasonic waves might not be applied thereon.
Here, in Prior Art (3) shown in
FIG. 12
, although it has a construction in which the upper second semiconductor chip
52
is made larger, the plane electrodes
68
of the second semiconductor chip
52
are formed within the range of the lower first semiconductor chip
51
in a limited manner in order to stabilize the wire bonding.
This construction, which has the plane electrodes
68
placed apart from the edge of the second semiconductor chip
52
, raises a problem in which elements on the periphery of the chip might be damaged or might contact the edge of the chip in a dicing process for dividing the wafer into semiconductor chips.
Therefore, it is not possible to adopt combinations in which either one of the chips is placed under the other with either of them sticking, such as a combination in which one of the chips virtually has a square shape with the other having a narrow rectangular shape.
Here, another technique is proposed in which a support member having the same thickness as the first semiconductor chip
51
is inserted to the lower portion of the second semiconductor chip
52
that is sticking out; however, this construction is not suitable because it is difficult to produce the support member having the same thickness with high precision and because complex processes cause high costs.
Moreover, even in the case when the upper second semiconductor chip
52
is smaller, if it is far smaller than the first semiconductor chip
51
, these can not be combined. In other words, wires
58
become too long, causing wire flow and wire deformation. When an attempt is made to connect the wires
58
at positions on the wiring layer
54
as closely as possible to the first semiconductor chip
51
, short-circuiting might occur due to contact with the edge of the first semiconductor chip
51
. In order to avoid this problem, when the wires
58
are connected at positions far from the first semiconductor chip
51
on the wiring layer
54
, the package size becomes larger.
SUMMARY OF THE INVENTION
The present invention relates to a semiconductor device for achieving a high density by la
Dotta Yoshihisa
Saza Yasuyuki
Tamaki Kazuo
Clark Jhihan B
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
LandOfFree
Semiconductor device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2843778