Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-12-11
2003-12-23
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S666000
Reexamination Certificate
active
06667235
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device having a size equivalent to that of a semiconductor element, and to a manufacturing method therefor.
2. Description of the Related Art
The configuration of an example of a conventional chip-size semiconductor device
10
is described using FIG.
5
.
Over a surface of a semiconductor element
12
on which electrode terminals
14
are formed, a passivation film
16
is formed, exposing the electrode terminals
14
.
On the passivation film
16
, an insulation coating
18
comprising an organic resin or the like is formed, exposing the electrode terminals
14
of the semiconductor element
12
.
On the insulation coating
18
is formed (a) wiring pattern(s)
20
, one end of which is electrically connected to an electrode terminal
14
of the semiconductor element
12
, and the other end of wiring pattern(s)
20
forms a land
20
a
. Item
20
b
is a conductive site which forms a part of the wiring pattern
20
that connects the land
20
a
to the electrode terminal
14
of the semiconductor element
12
.
On the surfaces of lands
20
a
, columnar electrodes
26
are arranged in an upright posture, and a sealing layer
28
is formed for sealing the wiring pattern
20
, while exposing the top end surfaces of the columnar electrodes
26
.
On the top end surfaces of the columnar electrodes
26
are formed plating layers
22
of nickel plating and gold plating, rendered successively.
Also, externally connecting terminals
24
are formed on the top end surfaces (that is, the surfaces of the plating layers
22
) of the columnar electrodes
26
, the top end surfaces being exposed out of the sealing layer
28
.
In a semiconductor device
10
such as this, when the semiconductor device
10
is mounted on a mounting board (not shown), the wiring pattern
20
tends to be subjected to stress owing to the difference in the coefficients of thermal expansion between the semiconductor element
12
and the mounting board (a resin circuit board, for example).
Thereupon, the columnar electrodes
26
having an elongated shape are interposed between the externally connecting terminals
24
and the wiring pattern(s)
20
, and the columnar electrodes
26
themselves absorb and ease that stress.
A summary of the manufacturing method for the semiconductor device
10
wherein a wiring pattern
20
is formed over the semiconductor element
12
as described above, is now described using
FIGS. 6
to
10
.
First, as diagrammed in
FIG. 6
, on the passivation film
16
that is on top of the semiconductor element
12
, the insulation coating
18
made of a polyimide resin is formed, excluding the sites for the electrode terminals
14
.
Next, as diagrammed in
FIG. 7
, a metal film
25
comprising an adhesive metal layer
25
a
made of titanium or chromium and a copper layer
25
b
is formed by sputtering so that the thicknesses of the layers
25
a
and
25
b
are on the order of approximately 0.05 to 0.2 &mgr;m and approximately 0.5 &mgr;m or so, respectively.
Next, as diagrammed in
FIG. 8
, a resist pattern
27
is formed in such a way that part of the copper layer
25
b
is left exposed for forming a wiring pattern (rewiring pattern) in the shape of groove, and, using this resist pattern
27
as a plating mask, and using the metal film
25
as a conductive layer, a plating film is formed by electrolytic copper plating on the metal film
25
to make the wiring pattern
20
. The metal layer formed by this electrolytic copper plating constitutes the basic part of the wiring pattern
20
.
After forming the wiring pattern
20
, the resist pattern
27
is removed.
Next, as diagrammed in
FIG. 9
, a plating resist layer
29
is formed over the semiconductor element
12
on which the wiring pattern
20
is formed, light exposure and developing are performed, a hole
31
is formed in the resist layer
29
, and the land
20
a
of the wiring pattern
20
is exposed.
Next, as diagrammed in
FIG. 10
, a plating film is formed by electroplating (copper, nickel, or the like) on the land
20
a
inside the hole
31
, and the columnar electrode
26
is formed (to a height of approximately 100 &mgr;m) by filling in the hole
31
.
Furthermore, on the top end surface of this columnar electrode
26
, a plating layer
22
comprising a nickel plating film and a gold plating film is formed. The plating layer
22
may also be a two-layer plating film wherein a nickel plating film and a palladium plating film are formed successively.
Next, the resist layer
29
is removed. Then, using the wiring pattern
20
as an etching mask pattern, etching is performed to remove the exposed metal film
25
(the copper layer
25
b
and adhesive metal layer
25
a
), thus making the wiring pattern(s)
20
independent.
In this manner, the insulation coating
18
, the wiring pattern(s)
20
, and the columnar electrodes
26
are formed on the semiconductor element
12
(FIG.
10
).
Next, as diagrammed in
FIG. 11
, over the surface of the semiconductor element whereon the electrode terminals
14
are formed, the sealing layer
28
for sealing that semiconductor element surface is formed, using a resin having electrically insulative properties.
To describe this in greater detail, the sealing layer
28
is formed in such a way that the top end surface of the columnar electrodes
26
is exposed. Externally connecting terminals
24
such as solder balls, for example, are joined to the top end surfaces of the columnar electrodes
26
exposed out of the sealing layer
28
.
The process steps up to this point are usually performed on a semiconductor wafer whereon a plurality of semiconductor elements are formed.
Then, last of all, the wafer is cut out into separate pieces according to respective semiconductor elements, so that the semiconductor device
10
diagrammed in
FIG. 5
can be manufactured.
FIG. 13
is a perspective view of one example of a semiconductor device manufactured in this way.
FIG. 14
is a sectional side view of one example of a semiconductor device manufactured in this way. In this case, no columnar electrodes are installed.
FIG. 15
is a diagram of one example of a semiconductor device manufactured in this way, viewed from the top.
This figure is rendered so that the wiring pattern, etc. can be seen through the sealing layer.
In the semiconductor device
10
described above, since the coefficients of thermal expansion differ greatly between the semiconductor element
12
and the sealing layer
28
coating over and sealing the top of the surface of the semiconductor element
12
whereon the electrode terminals are formed (electrode terminal forming surface of the semiconductor element
12
), it is considered to be necessary that the sealing layer
28
should not be easily peeled away from the adhesion surface thereof by the temperature fluctuation.
In the conventional semiconductor device
10
, the sealing layer
28
is held onto the top of the electrode terminal forming surface of the semiconductor element
12
by two adhesive forces, namely the adhesive force between the sealing layer
28
and the insulation coating
18
formed over the electrode terminal forming surface of the semiconductor element
12
, and the adhesive force between the wiring pattern
20
and the sealing layer
28
.
Also, because the adhesive force between resin layers is the larger of these two adhesive forces, the greater part of the overall adhesive force is accounted for by the adhesive force between the insulation coating
18
formed of a polyimide resin or the like and the sealing layer
28
.
However, as the number of the electrode terminals
14
on the semiconductor element
12
has been increasing, and the area of the wiring pattern(s)
20
formed over the electrode terminal forming surface has been increasing due to the miniaturization and the implementation of higher densities in recent years, the proportion of the exposed portion of the insulation coating
18
declines, resulting in a problem of a declined adhesive force of the sealing layer
28
over the el
Cao Phat X.
Shinko Electric Industries Co. Ltd.
Staas & Halsey , LLP
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