Semiconductor device, and manufacturing method therefor

Details Semiconductor device, and manufacturing method therefor Semiconductor device, and manufacturing method therefor

1999-03-12

2001-05-08

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S639000, C438S640000

Reexamination Certificate

active

06228755

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device having a multilayer wiring structure and to a manufacturing method therefor. More particularly, the present invention relates to a semiconductor device having a buried multilayer structure as well as to a manufacturing method suitable for manufacturing the same.
2. Description of the Background Art
FIGS. 16A
to
16
F are cross-sectional views for describing a method of manufacturing a former semiconductor device having a buried multilayer wiring structure. This manufacturing method will hereinafter be referred to as a “first former method.” In
FIGS. 16A and 16B
, reference numeral
10
designates an interlayer insulating film;
12
designates a lower wiring pattern;
14
designates a connection hole stopper film;
16
designates a lower interlayer insulating film;
18
designates an upper trench stopper film;
20
designates a resist mask for use in forming a connection hole (hereinafter referred to simply as a “resist mask”);
21
designates an upper interlayer insulating film;
22
designates a resist mask for use in forming an upper trench (hereinafter referred to simply as an “upper trench resist mask”);
24
designates a connection hole;
26
designates an upper wiring trench; and
28
designates conductive material.
Under the first former method, after the lower wiring pattern
12
has been formed on the interlayer insulating film
10
, the connection hole stopper film
14
is formed so as to cover the lower wiring pattern
12
. Subsequently, the lower insulating film
16
and the upper trench stopper film
18
are formed, in this sequence, on the connection hole stopper film
14
(see
FIG. 16A
) Next, the resist mask
20
is formed on the upper trench stopper film
18
by means of photolithography. Through dry etching, a connection hole is formed in the upper trench stopper film
18
(see FIG.
16
B).
The resist mask
20
is removed, and an upper insulation film
21
is formed on the upper trench stopper film
18
(see FIG.
16
C).
The upper trench resist mask
22
is formed on the upper insulating film by means of photolithography. The upper wiring trench
26
is formed in the upper insulating film
21
by means of dry etching. At this time, as a result of simultaneous removal of the portion of the lower insulating film
16
underlying the bottom of the connection hole formed in the upper trench stopper film
18
, a connection hole
24
is formed in a self-aligned manner until it reaches the connection hole stopper film
14
(see FIG.
16
D).
After removal of the upper trench resist mask
22
followed by removal of the exposed connection hole stopper film
14
at the bottom of the connection hole
24
, conductive material
28
is deposited in the connection hole
24
and the upper wiring trench
26
as well as on the upper insulating film
21
(see FIG.
16
E).
Finally, only the conductive material
28
deposited on the upper insulating film
21
is removed by means of Chemical-and-Mechanical Polishing (CMP), thereby resulting in formation of a desired structure (see FIG.
16
F). As mentioned above, according to the first former method, on a semiconductor substrate there can be formed a multilayer wiring structure comprising a plurality of wiring layers between which continuity is established at predetermined locations.
FIGS. 17A
to
18
D are cross-sectional views for describing a method of manufacturing a former semiconductor device having a buried multilayer wiring structure disclosed in Japanese Patent Application Laid-open No. 8-335634. This method will be hereinafter referred to as a “second former method.” In
FIGS. 17A through 18D
, reference numeral
12
designates a lower wiring pattern;
20
designates a resist mask for use in forming a connection hole;
22
designates a resist mask for use in forming an upper trench (hereinafter referred to simply as an “upper trench resist mask”);
24
designates a connection hole;
26
designates an upper wiring trench;
28
designates conductive material;
30
designates an interlayer insulating film; and
32
designates an organic compound.
Under the second former method, after formation of the interlayer insulating film
30
on the lower wiring pattern
12
, the resist mask
20
is formed on the interlayer insulating film
30
by means of photolithography (see FIG.
17
A).
The connection hole
24
is formed by means of dry etching so as to penetrate the interlayer insulating film
30
until it reaches the lower wiring pattern
12
. After formation of the connection hole
24
, the resist mask
20
is removed (see
FIG. 17B
) The organic compound
32
, which has an etching selectivity ratio of 0.5 or less with respect to the interlayer insulating film
30
is deposited on the interior of the connection hole
24
and on the interlayer insulating film
30
(see FIG.
17
C).
The organic compound
32
is removed from the top of the interlayer insulating film
30
in such a way that the organic compound
32
is left solely in the connection hole
24
(see FIG.
17
D).
The resist mask
22
is formed on the interlayer insulating film
30
by means of photolithography. The resist mask
22
is patterned in such a way that an opening is formed in a location on the resist mask
22
corresponding to an area including the connection hole
24
, i.e., an area including the remaining organic compound
32
(see FIG.
18
A).
After formation of the resist mask
22
, the interlayer insulating film
30
is etched to a predetermined depth by means of dry etching. As a result, the upper wiring trench
26
is formed (see FIG.
18
B).
The organic compound
32
still remaining in the connection hole
24
and the resist mask
22
are simultaneously removed (see FIG.
18
C).
Finally, a desired structure is formed by deposition of the conductive material
28
on the connection hole
24
and in the upper wiring trench
26
(see FIG.
18
H). As mentioned above, even under the second former method, there can be formed a multilayer wiring structure comprising a plurality of wiring layers between which continuity is established at predetermined locations.
However, under either of the first and second former method, in a case where a connection hole has a wide aspect ratio—particularly, where the aspect ratio exceeds a value of 2.5—or in a case where a connection hole has a small diameter,—particularly, where the diameter is 0.28 &mgr;m or less—conductive material cannot be correctly filled into the connection hole. For this reason, in a case where the multilayer wiring structure is sufficiently miniaturized, the former manufacturing method poses a problem of a contact failure being apt to arise between an upper wiring layer and a lower wiring layer.
Accurate formation of a multilayer wiring structure to be incorporated into a semiconductor device becomes important for pursuit of miniaturization of the semiconductor device. As in the case with the foregoing first former method, etching the lower interlayer insulating film
16
or the upper interlayer insulating film
21
through use of the connection hole stopper film
14
and the upper trench stopper film
18
is effective in accurately forming a multilayer wiring structure to be incorporated in the semiconductor device.
However, a silicon nitride film has a dielectric constant greater than that of a silicon oxide film. For this reason, existence of a silicon nitride layer in the multilayer wiring structure results in an increase in the interlayer capacitance of the silicon substrate. The operating speed of the semiconductor device decreases as an interlayer capacitance of the semiconductor device increases. For this reason, depending on the former semiconductor device manufacturing method, it is not necessarily easy to accurately fabricate a multilayer wiring structure while imparting a superior high-speed operating characteristic to the semiconductor device.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the previously-mentioned problems, and a general

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