Semiconductor device and manufacturing method of the same

Details Semiconductor device and manufacturing method of the same Semiconductor device and manufacturing method of the same

2009-01-15

2010-12-21

Stark, Jarrett J (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S176000, C438S294000, C257S407000, C257SE21195

Reexamination Certificate

active

07855134

ABSTRACT:
Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.

REFERENCES:
patent: 7265428 (2007-09-01), Aoyama
patent: 2007/0105317 (2007-05-01), Nakajima
patent: 2007/0126062 (2007-06-01), Akiyama et al.
patent: 2007/0178634 (2007-08-01), Jung et al.
patent: 2007/0210351 (2007-09-01), Tsuchiya et al.
patent: 2008/0157205 (2008-07-01), Sung et al.
patent: 2008/0274598 (2008-11-01), Ramin et al.
patent: 2005-294799 (2005-10-01), None
patent: 2007-141889 (2007-06-01), None
patent: 2007-142153 (2007-06-01), None
patent: 2007-242894 (2007-09-01), None
Inoue, M., et al., “Fluorine Incorporation into HfSiON Dielectric for VthControl and its Impact on Reliability for Poly-Si Gate pFET”, International Electron Devices Meeting Technical Digest, 2005, pp. 425-428, Washington DC, USA.
Hayashi, T., et al., “Cost Worthy and High Performance LSTP CMIS; Poly-Si/HfSiON nMIS and PolySi/TiN/HfSiON pMIS”, International Electron Devices Meeting Technical Digest, 2006, pp. 247-250, San Francisco CA, USA.
Narayanan, V., et al., “Band-Edge High-Performance High /Metal Gate n-MOSFETs using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond”, Symposium on VLSI Technology Digest of Technical Papers, 2006, pp. 224-225.

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