Semiconductor device and manufacturing method of the same

Active solid-state devices (e.g. – transistors – solid-state diode – Including semiconductor material other than silicon or... – Containing germanium – ge

Reexamination Certificate

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C257S368000, C257S617000, C257SE29297

Reexamination Certificate

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07436046

ABSTRACT:
Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1×1019cm−3or less.

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patent: 7141477 (2006-11-01), Noda
patent: 7172935 (2007-02-01), Lochtefeld et al.
patent: 9-321307 (1997-12-01), None
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patent: 2004-39762 (2004-02-01), None

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