Semiconductor device and manufacturing method of the same

Details Semiconductor device and manufacturing method of the same Semiconductor device and manufacturing method of the same

2007-04-17

2007-04-17

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257S344000, C257S408000, C257S369000

Reexamination Certificate

active

11049694

ABSTRACT:
In consideration of an optimum combination of impurities used for the purpose of forming an extension region (13) and a pocket region (11) and further inhibiting impurity diffusion in the extension region (13) when an impurity diffusion layer (21) is formed in a semiconductor device having an nMOS structure, at least phosphorus (P) is used as an impurity in the extension region (13), at least indium (In) is used as an impurity in the pocket region (11), and additionally carbon (C) is used as a diffusion inhibiting substance. Consequently, it is possible to easily and surely realize the scaling down/high integration of elements while improving threshold voltage roll-off characteristics and current drive capability and reducing a drain leakage current especially in the semiconductor device having the nMOS structure, and particularly by making the optimum design of a semiconductor device having a CMOS structure possible, improve device performance and reduce power consumption.

REFERENCES:
patent: 6380053 (2002-04-01), Komatsu
patent: 10-125916 (1998-05-01), None
patent: 11-87706 (1999-03-01), None
Y. Momiyama et al., Lateral Extension Engineering using Nitrogen Implantation (N-tub) for High-Performance 40-nm pMOSFETs, IEDM Technical Digest, pp. 647-650, 27.3, (2002).

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