Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2001-04-23
2004-09-14
Cuneo, Kamand (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
Reexamination Certificate
active
06791195
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a high-density type semiconductor device (HDP: High Density Package) of a flip-chip method, a semiconductor device (especially, CSP: Chip Size (Scale) Package) including an HDP mounted on an interposer and a multi chip module (MCM: Multi Chip Module, stacked MCP: Multi Chip Package) including a plurality of HDPs, and a manufacturing method thereof.
2. Description of the Related Art
In recent years, research and development work has been conducted on a higher density of mounting in a semiconductor device, and a number of structures and methods have been proposed for package forms or mounting methods. The forms are transitioning from QFPs (Quad Flat Package) which are a typical conventional semiconductor package to BGA (Ball Grid Array) packages of an area array type in response to the needs of an increase in number of pins and a reduction in size and weight. A high-density semiconductor package called a CSP with a reduced package size substantially equal to a chip size has been employed often in electrical equipment of small size.
At present, three kinds of interposers are mainly used in these BGA and CSP: a wiring tape made of polyimide or the like, a printed circuit board of a printed wiring board type made of glass epoxy or the like, and a ceramic substrate. The interposers serve to electrically and mechanically connect a semiconductor chip with a substrate on which the chip is to be mounted.
A flip chip technique is an ideal technique for mounting semiconductor chips onto an interposer at a high density. FIG.
1
(
a
) is a cross section of a conventional flip chip BGA using the flip chip technique. The flip chip technique employs semiconductor device
1
having bumps (projecting electrodes)
13
formed on electrodes
12
of semiconductor chip
11
. Bumps
13
are made of Au, Cu, Pb—Sn or the like, and formed with photolithography and plating. Semiconductor device
1
is bonded face down to interposer
14
. At that point, bumps
13
are electrically connected through metal junction to bonding pads
16
formed at respective portions of copper wiring
15
on the surface of interposer
14
. According to the flip chip technique, an increased number of pins, a reduced area for mounting, a higher speed of signal processing can be realized in semiconductor chips.
In such flip chip mounting, however, a difference in thermal expansion between semiconductor chip
11
and interposer
14
may concentrate stress on the junctions between semiconductor device
1
and interposer
14
to cause faulty connections when semiconductor device
1
is mounted on interposer
14
. For this reason, sufficient reliability is difficult to ensure. It is thus essential that efforts are made to ensure reliability of mounting and a defective item after mounting can be replaced individually.
To ensure such mounting reliability, an underfill technique has been developed for filling a protection resin between semiconductor chip
11
and interposer
14
. FIG.
1
(
b
) is a cross section of a conventional flip chip BGA using the flip chip technique and the underfill technique. The underfill technique is realized such that after semiconductor device
1
is mounted on interposer
14
, underfill resin
17
such as an epoxy resin is filled between semiconductor chip
11
and interposer
14
to protect the surface of semiconductor chip
11
and to reinforce the surroundings of bumps
13
, thereby achieving higher reliability of connection.
The underfill technique, however, involves a problem in that a smaller pitch of electrodes
12
(fine pitch), an accompanying smaller size of bumps
13
, and a smaller gap between semiconductor chip
11
and interposer
14
result in difficulties in completely filling underfill resin
17
between semiconductor chip
11
and interposer
14
and in checking whether or not any unfilled portion (void) is present after mounting.
A method capable of solving such a problem is disclosed, for example, in Japanese Patent Laid-open Publication No. 5-3183. In the method disclosed in Japanese Patent Laid-open Publication No. 5-3183, as shown in
FIG. 2
, bumps
13
are first provided on electrodes
12
of many semiconductor chips
11
which are allocated to semiconductor wafer
20
(FIG.
2
(
b
)). Next, a resin is applied to the surface of semiconductor wafer
20
(semiconductor chip
11
) to form protection film
18
. Then, protection film
18
is cured (
FIG. 2
(
c
)). Next, the back of semiconductor wafer
20
(semiconductor chip
11
) is polished to thin the chip (FIG.
2
(
d
)). Protection film
18
is polished to expose the surfaces of bumps
13
, thereby completing semiconductor device
2
.
When semiconductor device
2
is mounted on an interposer, bumps are provided also on the interposer for bonding to bumps
13
.
In this method, the surface of semiconductor chip
11
is covered and protected securely. Only good items can be mounted on an interposer by performing electrical selection, and the method is suitable for providing a smaller thickness since the polishing of semiconductor wafer
20
(semiconductor chip
11
) after the formation of protection resin
18
can produce a thin chip of up to approximately 50 &mgr;m. In addition, even when any defect occurs after the mounting on an interposer, replacement is readily made individually since the device is not completely fixed to the interposer by an epoxy resin or the like.
On the other hand, Japanese Patent Laid-open Publication No. 11-26642 discloses a method in which semiconductor device
70
having bumps
80
, adhesive sheet
98
having through-holes
102
, and interposer
72
B having connection holes
96
are manufactured individually before they are assembled. According to the method, after bumps
80
are aligned with connection holes
96
, adhesive sheet
98
is interposed between semiconductor device body
70
and interposer
72
B such that through-holes
102
are interposed between opposing bumps
80
and connection holes
96
. Semiconductor device
70
is pressed against interposer
72
B, bumps
80
are passed through through-holes
102
and connected to connection holes
96
, and they are bonded and fixed to each other (see FIG.
3
).
In addition, Japanese Patent Laid-open Publication No. 11-26642 discloses a method in which an anisotropic conductive film is used instead of adhesive sheet
98
.
Japanese Patent Laid-open Publication No. 8-102474 discloses a method in which after an adhesive is applied to a main surface of a semiconductor chip on which electrodes are formed, part of the adhesive on the electrodes is removed to form holes in the adhesive layer through which the electrodes are exposed, and then bumps are filled into the holes. According to the method, the adhesive layer is formed of a photosensitive resin such as polyimide or epoxy on the entire one surface of the semiconductor wafer, and the holes are formed through chemical etching in the portions of the adhesive layer where the electrode pads are to be exposed. Then, metal such as Au is filled into the holes through plating or the like.
The aforementioned prior arts, however, have the following problems.
In the method disclosed in Japanese Patent Laid-open Publication No. 5-3183, bumps
13
and semiconductor chip
11
fixed by protection film
18
provide reliability in the junction surface of semiconductor chip
11
and bumps
13
at the time of mounting on a substrate. In mounting on various interposers, however, sufficient reliability cannot be ensured for bonding to such interposers. Also, thinner semiconductor chip
11
may cause thermal stress and warp stress applied to semiconductor chip
11
from the junction to destroy semiconductor chip
11
itself. This is because thermal stress and mechanical stress at the time of mounting on various interposers applied only to connection terminals (bumps) result in high dependence on the arrangement of the terminals, the number of pins, the si
Cuneo Kamand
Geyer Scott B.
McGinn & Gibb PLLC
NEC Electronics Corporation
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