Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2000-08-10
2002-09-24
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S184000, C438S581000, C438S583000
Reexamination Certificate
active
06455361
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods of the same, particularly to those suitably applied to metal semiconductor field-effect transistors (hereinafter referred to as MESFETs) and high electron mobility transistors (hereinafter referred to as HEMTS) using compound semiconductors.
2. Description of the Related Art
MESFETs and HEMTs, which are semiconductor devices using compound semiconductors such as GaAs and InP, are used as amplifying devices for high frequency bands, or devices for making up ultra high-speed integrated circuits. At present, in order to obtain higher-speed operation of such devices, shortening of gate length is being developed. Such shortening of gate length requires reduction in source resistance and control of short channel effect.
For example, in a GaAs-base MESFET, as shown in
FIG. 19
, an ion implantation method is used for forming conductive layers which are to serve as source/drain regions. In addition to the ion implantation for the source/drain regions
101
and
102
, shallow implantation regions
104
and
105
are formed in the vicinity of the gate electrode
103
in a self-alignment manner with the gate electrode
103
, in order to reduce the source resistance.
In such a GaAs-base MESFET as shown in
FIG. 19
, formation of a low-resistance layer requires a high-temperature treatment at a temperature in the extent of 700° C. to 800° C. for annealing to activate carriers after ion implantation. This causes the problem that gate characteristics of the gate electrode
103
in relation to the GaAs substrate
111
may deteriorate due to a thermal diffusion. Besides, because the conductive layer thus formed by ion implantation is not sufficiently shallow, also the problem that a short channel effect appears in a shortened gate length to degrade device characteristics, cannot be neglected.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide semiconductor devices using compound semiconductors, including source and drain regions (at least one of them) easily formed with a shallow junction depth without using any ion implantation, wherein occurrence of short channel effect is prevented even in their reduced device size as a result of their shortened gate electrodes, so as to obtain excellent device characteristics.
It is another object of the present invention to provide manufacturing methods of such semiconductor devices.
A semiconductor device according to the present invention comprises a gate electrode on a compound semiconductor substrate and source/drain regions in the compound semiconductor substrate. In particular, the semiconductor device has a MESFET or HEMT structure. In this semiconductor device, at least one of the source/drain regions is made of a solid-phase reaction layer of the compound semiconductor and a specific metal, and electrodes electrically connected to the source/drain regions are provided independently of the solid-phase reaction layer.
In this case, the specific metal is preferably one selected among Ti, Co, Ni, Pd and Mo.
A manufacturing method according to the present invention is for such a semiconductor device. More specifically, the method comprises the steps of: forming a gate electrode by patterning on a channel layer formed on a compound semiconductor substrate; forming a specific metal film so as to cover at least one of side portions. of the gate electrode on the compound semiconductor substrate; reacting the compound semiconductor with the specific metal in solid phase to form at least one solid-phase reaction layer in the compound semiconductor substrate; and removing the part of the specific metal film which has not been reacted, so that at least one of the source/drain regions is made of the solid-phase reaction layer.
In this case, the specific metal film is; preferably formed so as to cover the upper and side portions of said gate electrode, so that the solid-phase reaction layer is formed in a self-alignment manner with the gate electrode.
The depth of the solid-phase reaction layer can be locationally controlled by a locational control of the depth of the specific metal film.
The part of said film which has not been reacted can be removed by etching, such that the gate length of the gate electrode is shortened in the etching process.
The specific metal film can be formed so as to have its thickness at a portion near the gate electrode larger than its thickness on the periphery of the portion.
According to an aspect of the present invention, either side of the gate electrode is covered with an insulating material, and the specific metal film is formed in this state.
According to the present invention, formation of a conductive layer to serve as a source or drain is performed by reacting a compound semiconductor with a specific metal in solid phase, without using any ion implantation method. In this case, since a temperature lower than that for an annealing treatment after the ion-implantation suffices for the thermal treatment for the solid-phase reaction, excessive thermal diffusion of carriers in the solid-phase reaction layer can be controlled, and hence a very shallow junction can be formed. This junction depth can be regulated with a high precision by adjusting the thickness of the specific metal film, and the source and/or the drain can be formed to a desired junction depth with a high precision in coping with a shortened gate electrode.
According to the present invention, therefore, semiconductor devices using compound semiconductors can be realized in which their sources and drains (or at least one of them) can be very easily formed to a shallow junction depth without using any ion implantation process, and,occurrence of short-channel effect can be suppressed even in their reduced device size as a result of their shortened gate electrodes, thus achieving excellent device characteristics.
REFERENCES:
patent: 5217923 (1993-06-01), Suguro
Nihei Mizuhisa
Watanabe Yuu
Armstrong Westerman & Hattori, LLP
Chaudhuri Olik
Doan Theresa T.
Fujitsu Limited
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