Semiconductor device and manufacturing method of same

Details Semiconductor device and manufacturing method of same Semiconductor device and manufacturing method of same

2009-03-11

2011-12-13

Pert, Evan (Department: 2893)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C257S347000, C257S353000, C257S618000, C257S628000, C257SE21377, C438S153000, C438S154000, C438S585000

Reexamination Certificate

active

08076231

ABSTRACT:
A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

REFERENCES:
patent: 7564081 (2009-07-01), Zhu et al.
patent: 7812398 (2010-10-01), Saito et al.
patent: 2007/0190708 (2007-08-01), Kaneko et al.
patent: 2007/0210355 (2007-09-01), Izumida
patent: 2007-158329 (2007-06-01), None
patent: 2007-207837 (2007-08-01), None
K. Ota, et al., “Novel Locally Strained Channel Technique for High Performance 55nm CMOS”, Technical Digest of International Electron Devices Meeting (IEDM), 2002, 4 pages.

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