Semiconductor device and manufacturing method of same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S315000, C257S316000, C438S257000

Reexamination Certificate

active

07633113

ABSTRACT:
A semiconductor device in which a channel region of MOS transistor is provided not to include a non-flat active region end portion and a manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor device comprising a semiconductor substrate, a device isolation separating active region, wherein at least a portion of the device isolation is provided in the semiconductor substrate, and a memory cell including a memory cell transistor that comprises a channel region separated by a slit and constituted of a flat active region alone, a charge storage layer provided on a gate dielectric on the channel region, and a first gate electrode provided on an inter-electrode dielectric so as to cover the charge storage layer, and a select transistor that comprises a second gate electrode provided on the gate dielectric on the active region and electrically connected to a wiring.

REFERENCES:
patent: 6555427 (2003-04-01), Shimizu et al.
patent: 2006/0234448 (2006-10-01), Yonehama et al.
patent: 2001-94075 (2001-04-01), None
patent: 2004-48064 (2004-02-01), None
K. Shimizu, et al., “A Novel High-Density 5F2NAND STI Cell Technology Suitable for 256Mbit and 1Gbit Flash Memories”, IEEE Tech. Dig. of IEDM, 1997, 4 pages.
Albert Fazio, “A 130nm Flash+Logic: Technology and Applications”, IEEE Proc. NVSMW, 2003, pp. 12-14.
Wook Hyun Kwon, et al., “Highly Reliable 256Mb NOR Flash MLC with Self-Aligned Process and Controlled Edge Profile”, Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials, 2005, pp. 448-449.

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