Semiconductor device and its production process

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C257S762000

Reexamination Certificate

active

06569767

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a process for producing the same. More particularly, it relates to a semiconductor device and its production process which allows direct bonding of a wire on a metal wiring layer containing copper as a main component without need to form an aluminum pad for bonding.
2. Description of Related Art
A metal wiring layer containing copper is of low electric resistance and exhibit good resistance to migration. For this reason, it can reduce signal delay owing to the metal wiring layer in a integrated circuit of a semiconductor device. Especially when the semiconductor device is operated at high-density current, the metal wiring layer containing copper can ensure high reliability. From this viewpoint, copper has begun to be used as a material for the metal wiring layer in place of aluminum.
At present, the metal wiring layer containing copper is used mainly in the semiconductor device having a high-speed logic circuit such as a microprocessor. For packaging the semiconductor device, utilized is a flip-chip technique in which a bump is formed on the semiconductor device (semiconductor chip). In the semiconductor device for general use, bonding is performed using a wire of gold or aluminum. This bonding involves heating at about 200° C. at the lowest. Since copper is easily oxidized to its inside at this temperature, it is difficult to perform the bonding without affecting the quality of the devices.
To cope with this inconvenience, proposed are methods of providing an aluminum pad on the metal wiring layer of copper with or without intervention of a diffusion-barrier layer of metal (see Japanese Unexamined Patent Publications Nos. HEI 8(1996)-78410 and HEI 11(1999)-135506).
One example of the above-mentioned methods is now explained with reference to FIGS.
3
(
a
) to
3
(
e
).
A diffusion layer
10
is formed on a silicon substrate
1
, and thereafter, an insulating film is formed of SiO
2
, SiN or the like as an interlayer dielectric film
2
. Subsequently, a contact hole is opened in the interlayer dielectric film
2
. An adhesion promoting layer
4
is formed of TiN by CVD for enhancing the adhesion of the interlayer dielectric film
2
to a copper wiring layer
5
formed later. This adhesion promoting layer
4
also functions as a diffusion-barrier film for preventing diffusion of copper from the copper wiring layer
5
to the interlayer dielectric film
2
. By forming a copper film on the adhesion promoting layer
4
by DC sputtering, the contact hole is filled with a copper film
5
′ (see FIG.
3
(
a
)).
Subsequently, an anti-reflection film
11
is formed on the copper film
5
′ (see FIG.
3
(
b
)).
Next, the copper film
5
′ is formed into the copper wiring layer
5
having a desired pattern by photolithography step and etching step. Subsequently, a surface protection film
12
is formed of an insulating film such as of SiO
2
, SiN or the like on the surface of the copper wiring layer
5
. Further, the surface protection film
12
and the anti-reflection film
11
are selectively removed to expose a part of the copper wiring layer
5
. Thus a pad region
7
a
is opened (see FIG.
3
(
c
)).
After the pad region
7
a
is opened, a diffusion-barrier layer
3
such as of TiN and an oxidation-resistant metal film
13
such as of AlSiCu are formed in thicknesses of about 20 to 100 nm and about 2 &mgr;m, respectively, in the opening of the pad region
7
a
. Subsequently, the diffusion-barrier layer
3
and the oxidation-resistant metal film
13
are left existing only in the vicinity of the pad region
7
a
(FIG.
3
(
d
)).
By adopting this construction in which the copper wiring layer
5
in the pad region
7
a
is covered with the oxidation-resistant metal film
13
, it is possible to prevent the oxidation of the copper wiring layer
5
during bonding not only by ultrasonic wire bonding, according to which a bonding face is heated to 200° C. or higher, but also by thermocompression wire bonding, according to which the bonding face is heated to 400° C. or higher. FIG.
3
(
e
) illustrates a state in which a wire
8
is bonded in the pad region
7
a.
FIG. 4
is a schematic sectional view of an example of semiconductor device having two copper-containing wiring layers to which a wire is bonded as disclosed by Japanese Unexamined Patent Publication No. HEI 11(1999)-135506. This semiconductor device is produced as follows; first, a copper wiring layer
5
b
formed by a damascene method is covered with an insulating film
6
, and a bonding pad portion is opened. Thereafter, the insulating film
6
is covered with an aluminum-containing film
9
, and the aluminum-containing film
9
is partially removed by photolithography step and etching step so as to remain in the bonding pad portion; next, a wire
8
of gold, aluminum or the like is bonded to the bonding pad portion. In the figure,
2
a
to
2
d
denote interlayer dielectric films,
3
a
to
3
c
diffusion-barrier films,
4
a
and
4
b
copper-diffusion-barrier films and
5
a
a copper wiring layer.
In the method shown in FIGS.
3
(
a
) to
3
(
e
), the diffusion-barrier layer and the oxidation-resistant layer are formed on the entire surface, and then selectively removed by photolithography step and etching step in such a manner that they remain in the bonding pad portion. Accordingly, this method requires a large number of production steps, and involves an increase in production costs.
The method shown in
FIG. 4
, in which a pad of the aluminum-containing film is formed as a bonding pad on the copper wiring layer, requires the addition of the step of depositing either aluminum or aluminum and a diffusion-barrier metal, and a photolithography step and etching step or a chemical mechanical polishing step. For this reason, this method requires more production steps than aluminum interconnecting, and involves an increase in the production costs.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a process for producing a semiconductor device comprising the steps of: forming a metal wiring layer containing copper as the main component on a semiconductor substrate; forming an insulating film on the entire surface of the resulting semiconductor substrate; removing the insulating film only from a place where a wire of gold or aluminum is to be bonded, in order to expose a part of the metal wiring layer; forming a layer of copper silicide or a layer of a compound of copper and boron in a surface layer of the exposed part of the metal wiring layer; and bonding a wire to a surface of the layer of copper silicide or the layer of the compound of copper and boron.
Further, the present invention provides a semiconductor device comprising a metal wiring layer containing copper as a main component on a semiconductor substrate; and a layer of copper silicide or a layer of a compound of copper and boron for bonding a wire, the layer being formed in a surface layer of a part of the metal wiring layer.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 6181013 (2001-01-01), Liu et al.
patent: 6251775 (2001-06-01), Armbrust et al.
patent: 6303505 (2001-10-01), Ngo et al.
patent: 8-78410 (1996-03-01), None
patent: 11-135506 (1999-05-01), None

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