Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-07-11
2006-07-11
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000, C257S374000, C438S207000, C438S218000, C438S219000
Reexamination Certificate
active
07075149
ABSTRACT:
A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semiconductor base layer between the first semiconductor region and the first semiconductor pillar layer and between the first semiconductor region and the third semiconductor pillar layer, and provided on the second semiconductor base layer between the second semiconductor region and the third semiconductor pillar layer and between the second semiconductor region and the fifth semiconductor pillar layer; and gate electrode provided on the gate insulating film. Each width of the first through fifth semiconductor pillar layers seen in a perpendicular direction to interfaces of p-n junctions formed among the first through fifth semiconductor pillar layers respectively is 10 microns or less.
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Okumura Hideki
Sato Shingo
Tokano Kenichi
Yamashita Atsuko
Abraham Fetsum
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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