Semiconductor device and its manufacturing method

Details Semiconductor device and its manufacturing method Semiconductor device and its manufacturing method

2005-06-21

2005-06-21

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S382000, C257S760000, C257S068000, C257S069000, C257S074000

Reexamination Certificate

active

06909132

ABSTRACT:
In a contact structure having a large aspect ratio in a LSI device incorporating DRAM cells and logics, for the purpose of preventing over-etching of a device isolation insulating film and an impurity diffusion layer and thereby minimizing junction leakage, a first etching stopper layer covering a peripheral MOS transistor and a second etching stopper layer overlying a capacitor section of a DRAM memory cell are formed. An impurity diffusion layer of the peripheral MOS transistor is connected to a metal wiring layer formed in an upper level of the capacitor section by an electrode layer extending through the first and second etching stopper layers. At least one of such impurity diffusion layers is connected to the electrode layer at its boundary with the device isolation insulating film, and depth of the bottom of the electrode layer formed on the device isolation insulating film from the surface of the impurity diffusion layer is shorter than the junction depth of the impurity diffusion layer.

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patent: 6104059 (2000-08-01), Ono
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Hagiwara, “Microelectronics for Home Entertainment,” Society ESSCIR2001, Villach, Austria, Sep. 9, 2001 (9 pages).

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