Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-07-01
2004-08-03
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S773000, C257S774000, C257S763000, C257S764000, C257S765000
Reexamination Certificate
active
06770974
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and its fabricating method. Particularly, it relates to a semiconductor device in which a capacitance element is mounted on a semiconductor substrate and a method of fabricating the device.
BACKGROUND ART
A conventional process for fabricating LSI (Large-scale Integrated Circuit) where a capacitance element is formed on a semiconductor substrate will be described with reference to schematic sectional process diagrams of
FIG. 39
to FIG.
41
.
To start with, as shown in
FIG. 39
, a first insulation film
12
and a second insulation film
16
which are made of SiO
2
film or the like are piled in turn on a semiconductor substrate
10
.
Subsequently, using the sputtering method for example, on the second insulation film
16
are piled a Ti layer, a TiON layer, a Ti layer, an Al—Si layer and a TiN layer in turn from below to form a TiN/Al—Si/Ti/TiON/Ti lamination film.
Subsequently, using CVD (Chemical Vapor Deposition) method for example, on the TiN/Al—Si/Ti/TiON/Ti lamination film is piled a dielectric film of SiO
2
, SiN, Ta
2
O
5
and the like. Further, using the sputtering method for example, on the dielectric film is piled a conductor layer of a Ti layer, a TiN layer or the like.
Then, through the photolithographing process and RIT (Reactive Ion Etching) process, these piled conductor layer and dielectric film are selectively removed by etching into a predetermined pattern to form an upper electrode
22
of Ti, TiN and the like on the TiN/Al—Si/Ti/TiON/Ti lamination film through a dielectric film
20
of SiO
2
SiN, Ta
2
O
5
or the like.
Subsequently, through the photolithographing process and RIE process, the TiN/Al—Si/Ti/TiON/Ti lamination film
18
is selectively removed by etching into a predetermined pattern to form a lower electrode
18
d
of the TiN/Al—Si/Ti/TiON/Ti lamination film.
In this way, a capacitance element comprised of the upper electrode
22
and the lower electrode
18
d
which sandwich the dielectric film
20
between them is formed.
Subsequently, using the plasma CVD method for example, which uses TEOS (tetraethoxy silane; Si(OC
2
H
5
)
4
) as raw materials, a SiO
2
film is piled on the whole surface of a base body including the upper electrode
22
and lower electrode
18
d
. After the SiO
2
film is further coated with SOG (Spin On Glass) film, a smoothing process that etches back these SOG film and SiO
2
film is performed. In other words, unevenness of the surface of the base body is smoothed by filling with a smoothing insulation film
24
formed of the SiO
2
film and SOG film.
Note that, on this occasion, because the surface of the upper electrode
22
formed on the lower electrode
18
d
lies on a higher level than the surface of the lower electrode
22
, the surface of the upper electrode may have sometimes been in a exposed state.
Next, as shown in
FIG. 40
, using the plasma CVD method for example, an insulation film
26
made of, e.g. SiO
2
film is piled on the whole surface of the base body including the upper electrode
22
and the smoothing insulation film
24
. An inter-layer insulation film
27
is thus formed by the smoothing insulation film
24
and insulation film
26
.
Subsequently, using the photolithographing process and the dry etching method, the inter-layer insulation film
27
on the upper electrode
22
is selectively removed by etching and the inter-layer insulation film
27
on the lower electrode
18
d
is also selectively removed by etching to open a first via-hole
28
d
and a second via-hole
28
e
. At this time, in order to reduce a contact resistance, TiN in the surface of the lower electrode
18
d
may sometimes be removed.
Next, as shown in
FIG. 41
, after an Al-alloy layer is piled on the whole surface of the base body using the sputtering method for example, the Al-alloy layer is processed using the photolithographing process and the dry etching method to form a first Al-alloy upper layer wiring layer
30
d
and a second Al-alloy upper layer wiring layer
30
e
that are connected to the upper electrode
22
and the lower electrode
18
d
through the first and second via-holes
28
d
and
28
e
, respectively.
However, in the conventional process of forming a capacitance element, when the smoothing process to smooth unevenness of the surface of the base body by filling with the smoothing insulation film
24
formed of the SiO
2
film and SOG film is performed after a capacitance element comprised of the upper electrode
22
and lower electrode
18
d
that sandwich the dielectric film
20
between them is formed, because the surface of the upper electrode
22
formed on the lower electrode
18
d
lies on a higher level than the surface of lower electrode
18
d
, the upper electrode
22
and further, even the dielectric film
20
lying thereunder is subjected to etching by the etch-back in the smoothing process. That is to say, in the smoothing process, the upper electrode
22
and further the dielectric film
20
lying thereunder sustain damage.
Therefore, there is a problem in which characteristics of a capacitance element such as a capacitance value fluctuate or its reliability deteriorates, so that it is impossible to obtain such a capacitance element that has satisfactory characteristics and high reliability.
Moreover, when the first and second via-holes
28
d
and
28
e
are opened so as to form the first and second Al-alloy upper layer wiring layers
30
d
and
30
e
connected respectively to the upper electrode
22
and lower electrode
18
d
of a capacitance element, the film thickness of inter-layer insulation film
27
on the upper electrode
22
to be etched for opening the first via-hole
28
d
is thicker than the film thickness of inter-layer insulation film
27
on the lower electrode
18
d
to be etched for opening the second via-hole
28
e
. Thus, when the first and second via-holes
28
d
and
28
e
are both intended to be opened satisfactorily, excess over-etching on the surface of upper electrode
22
will inevitably take place. As a result, the upper electrode
22
or the dielectric film
20
lying thereunder will sustain damage due to the over-etching.
Consequently, this point also raises the problem in which the characteristics of capacitance element such as a capacitance value fluctuate or its reliability deteriorates, thus making it impossible to obtain such a capacitance element that has satisfactory characteristics and high reliability.
Furthermore, the following problem is also raised.
That is, in a conventional capacitance element, when comparison is made between distances from an area where the upper electrode
22
and lower electrode
18
d
are opposed to each other, which effectively functions as a capacitance element, to the first Al-alloy upper layer wiring layer
30
d
and to the second Al-alloy upper layer wiring layer
30
e
, the distance on the lower electrode side generally tends to be longer than that on the upper electrode side. As a result, the difference between their impedances occurs, thereby posing another problem of further adding to asymmetry in its characteristics.
When comparison is made between the first and second via-holes
28
d
and
28
e
in the conventional capacitance element, the depth of the second via-hole
28
e
on the lower electrode side is deeper than the depth of the first via-hole
28
d
on the upper side electrode side. This further increases the conventional asymmetry of its characteristics.
SUMMARY OF THE INVENTION
The present invention was made in view of the foregoing points at issue. An object of the present invention is to provide a semiconductor device and its fabricating method capable of preventing the fluctuation in characteristics such as capacitance value or deterioration of reliability by damage caused to the upper electrode or dielectric film during the process of fabricating a capacitance element, and further suppressing an increase of asymmetry in characteristics, thereby allowing a capacitance element with satisfactory characteristics and high re
Clark Jasmine
Sonnenschein Nath & Rosenthal LLP
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