Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-29
2004-01-06
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S296000, C257S412000, C257S413000, C257S390000
Reexamination Certificate
active
06674137
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a semiconductor device and its method of manufacture, and more particularly to a semiconductor device having a gate electrode with a high aspect ratio and a narrow pitch, preferably a dynamic random access memory (DRAM).
BACKGROUND OF THE INVENTION
It remains a continuing goal of semiconductor manufacturing to fabricate devices with smaller and smaller features. One such feature can include a transistor gate length. As gate lengths approach smaller and smaller sizes, transistors can suffer from the unwanted generation of hot carriers, which can lead to “short” channel effects. Short channel effects can reduce the reliability of transistors.
One approach to addressing reduced reliability from short channel effects can include reducing the electric field region in the vicinity of a transistor drain. A structure for reducing such an electric field can include a lightly doped drain (LDD). An LDD structure can include a region between a channel (situated below a transistor gate) and a source/drain region that has a lower impurity density than the source/drain region. Such a structure can result in a less severe, or milder impurity density than non-LDD structures. This can raise a punch-through voltage and/or hot carrier withstand voltage in a transistor, thus improving reliability.
Japanese Laid-Open Patent Application Nos. 226499/1995, 074196/1997 and 45995/1999 disclose a structure that includes an LDD region. In the disclosed structure, a silicon oxide film, a silicon nitride film, or a reoxidizied nitrided oxide (RNO) can be formed on a gate electrode side wall.
Japanese Laid-Open Patent Application No. 226499/1995 also discloses an oxide film that covers a gate electrode. The oxide film can improve product yield by recovering a damaged gate oxide film to an original condition.
Referring now to FIGS.
1
(
a
) to
1
(
d
), a series of cross sectional views are shown illustrating a conventional method for manufacturing a semiconductor device. The method of FIGS.
1
(
a
) to
1
(
d
) can correspond to that shown in Japanese Laid-Open Patent Application No. 226499/1995.
Referring now to FIG.
1
(
a
), a device isolation film (not shown) is formed on a semiconductor substrate
1
. Substrate
1
may be p-type silicon. A gate oxide film
5
may be formed in a field (or active) region with a thermal oxidation method. A field region may be surrounded by a device isolation film, which may include silicon oxide. Thereafter, polysilicon may be formed on the gate oxide film
5
with a reduced pressure chemical vapor deposition (CVD) method. A gate electrode
6
may be formed from the polysilicon with known photolithography and dry etching techniques.
Next, as shown in FIG.
1
(
b
), an oxide film
13
is formed that covers gate electrode
6
with a heat treatment in an oxygen atmosphere. As noted before, oxide film
13
can recover gate oxide film
5
that has been damaged.
Thereafter, as shown in FIG.
1
(
c
), an entire surface of a substrate
1
is implanted with low density ions, with ion implantation techniques. Gate electrode
6
may be an implant mask. Annealing under predetermined conditions may result in N− type source/drain region
3
.
Then, as shown in FIG.
1
(
d
), a silicon oxide film, etc., is deposited on the entire surface of the substrate
1
with reduced pressure CVD methods, or the like. The silicon oxide film may then be etched back with anisotropic dry etching to form side wall oxide film
14
on a side wall of gate electrode
6
. A high density ion implantation may then be performed with gate electrode
6
and side wall oxide film
14
as masks, to form N+ source/drain region
4
.
In a resulting structure, a low density impurity region (e.g., N− type source/drain region
3
) may be formed that is offset with respect to a gate electrode
6
. Such a low density impurity region may also be self-aligned with a gate electrode
6
, just under side wall oxide film
14
. At the same time, a high density impurity region may (e.g., N+ type source/drain region
4
) is formed on the outside of side wall oxide film
14
.
In a conventional approach like that described above, a substrate region below an end of a gate electrode
6
may not be implanted, and thereby not form a portion of a low density impurity region. This may be particularly true when a side surface film, such as an oxide film and/or nitride film, is formed on a side of a gate electrode
6
. Such a side surface film (like
13
) may block ions from penetrating into a substrate. Thus, a substrate region offset with respect to a gate electrode
6
is prevented from being effectively implanted. Due to such a non-implanted region, a resulting source/drain region may have a higher than desirable resistance, unduly slowing the speed of a metal-oxide-semiconductor (MOS) transistor.
To solve the problem of high resistance offset regions, a method is disclosed in Japanese Laid-Open Patent Application Nos. 074196/1997 and 012747/1998. The method shows forming N− type source/drain regions with a low density impurity implantation having a tilted implant angle. That is, impurities are implanted at a slant with respect to a normal line of a substrate. Such tilt implant approaches can address the problem of failing to implant close enough to a gate electrode for certain device features. However, as feature sizes shrink and/or are changed, such methods may not be sufficient.
As features sizes shrink, a width of a sidewall oxide film (such as that shown as
14
in FIG.
1
(
d
)) can also shrink. This may be desirable in order to increase a contact area. A smaller sidewall thickness, however, may translate into a smaller interval between a channel region and a higher density impurity region of a source/drain formed outside a side wall oxide film. This reduced interval may result in a leakage current due to a strong electric field at the end of a gate, and thus reduce the data retention times of a transistor.
In addition, in many cases a gate electrode
6
can have a laminated structure that includes a polysilicon layer and a silicide layer. Such laminated gate electrodes may have a greater height, further increasing an aspect ratio (height/width) of a gate electrode. The above noted problem of an undesirably narrow interval may be more conspicuous for higher aspect ratio structures.
To better understand the drawbacks to conventional approaches, a conventional manufacturing method for a semiconductor device will now be described with reference to FIGS.
2
(
a
)-
2
(
e
). FIGS.
2
(
a
)-
2
(
e
) show cross sectional views of a semiconductor device having structures with high aspect ratios.
Referring first to FIG.
2
(
a
), a device isolation film
2
is formed in a semiconductor substrate
1
. A semiconductor substrate
1
can comprise p type silicon, or the like, and a device isolation film
2
may be an oxide. A gate insulating film
5
comprising silicon oxide may be formed on a semiconductor substrate
1
with a thermal oxidation method. A gate insulating film
5
may cover a field region situated between device isolation films
2
. Thereafter, a polysilicon film
6
a
and silicide film
6
b
may be formed using a plasma CVD (PCVD) method, or the like. A mask nitride film
15
may then be formed. A mask nitride film
15
may serve as an etch stop that can prevent a silicide film
6
b
from being exposed in a side wall etch back step (described more below). A patterning step may then etch through a mask nitride film
15
, silicide film
6
b,
and polysilicon film
6
a
to form a gate electrode
6
. Such a patterning step includes known photolithography and dry etching steps.
In addition to protecting a gate
6
, during an etch back step that forms side wall oxide layers, a mask nitride film
15
can also serve as an etch stop in a self-aligned contact structure. In a self-aligned contact structure, a contact hole may overlap a gate electrode
6
. During a contact hole etching step, side wall oxide layers and top mask nitride film prevent a gate ele
Flynn Nathan J.
Mandala Jr. Victor A.
NEC Corporation
Sako Bradley T.
Walker Darryl G.
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