Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2009-03-24
2010-12-14
Barnie, Rexford N (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
Reexamination Certificate
active
07852111
ABSTRACT:
A 4-bit counter outputs a 4-bit counted value CNTp based on an up-and-down signal Sp supplied from a comparator. A weighting selection circuit performs weighting based on a deviation from an average value of the DC characteristic of each PMOS transistor, and assigns a transistor having the smallest deviation to Bit1(LSB) of the 4-bit counter. The weighting selection circuit assigns two PMOS transistors to Bit2of the 4-bit counter, four PMOS transistors to Bit3, and eight PMOS transistors to Bit4(MSB). Then, the weighting selection circuit selects transistors P3-1to P3-30based on the counted value CNTp output from the 4-bit counter.
REFERENCES:
patent: 7288959 (2007-10-01), Lee
patent: 2005039549 (2005-02-01), None
Barnie Rexford N
NEC Corporation
Tran Thienvu V
LandOfFree
Semiconductor device and impedance adjustment method of the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and impedance adjustment method of the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and impedance adjustment method of the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4174815