Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2011-08-09
2011-08-09
Estrada, Michelle (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S199000, C438S519000, C438S527000, C257SE21632, C257SE29012, C257SE29278, C257SE21435
Reexamination Certificate
active
07994040
ABSTRACT:
A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer. The opening is sealed by a sealing layer to form an air gap.
REFERENCES:
patent: 6893967 (2005-05-01), Wright et al.
patent: 7018888 (2006-03-01), Goodlin et al.
patent: 7217626 (2007-05-01), Bu et al.
patent: 2002/0160592 (2002-10-01), Sohn
patent: 2008/0182372 (2008-07-01), Liu et al.
Chen Chang-Ku
Chi Min-hwa
Chiang Mu-Chi
Chiang Wen-Chuan
Birch & Stewart Kolasch & Birch, LLP
Estrada Michelle
Taiwan Semiconductor Manufacturing Co. Ltd.
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