Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Entirely of metal except for feedthrough
Reexamination Certificate
2001-10-22
2003-07-01
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Entirely of metal except for feedthrough
C257S729000
Reexamination Certificate
active
06586832
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device constructed such that a semiconductor chip is bonded to a surface of a solid device such as a wiring board or a second semiconductor chip.
2. Description of Related Art
Semiconductor devices of a flip chip bonding structure are hitherto known which, for example, have a semiconductor chip bonded to a surface of a wiring board with its face down. In such a flip-chip semiconductor device, the semiconductor chip is bonded to the wiring board with an active surface thereof being opposed to the wiring board. The semiconductor chip is physically and electrically connected to the wiring board in a predetermined spaced relation by a plurality of bumps provided between the semiconductor chip and the wiring board. Solder balls are provided as terminals for external connection on a rear surface of the wiring board. Where the number of the terminals are relatively great, the wiring board has a greater size than the semiconductor chip as viewed in plan. Therefore, a metal stiffener is provided as surrounding the periphery of the semiconductor chip to keep the planarity of the wiring board.
The semiconductor device having the aforesaid construction is fabricated, for example, by first bonding the semiconductor chip onto the wiring board and then providing the stiffener (which is a separate member from the semiconductor chip) on the wiring board. Therefore, the semiconductor chip and the stiffener, if each having a small thickness, are liable to be cracked or chipped during handling thereof for mounting thereof on the wiring board. This poses limitations to thickness reduction of the semiconductor chip and the stiffener and, hence, to thickness reduction of the entire semiconductor device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device constructed so that fabrication thereof can be achieved without cracking and chipping of a semiconductor chip or a stiffener.
It is another object of the present invention to provide a fabrication process for a thin semiconductor device, which is free from cracking and chipping of a semiconductor chip and a stiffener.
The semiconductor device according to the present invention comprises: a semiconductor chip bonded to a surface of a solid device; and a stiffener surrounding the periphery of the semiconductor chip with a surface thereof opposite from the solid device being generally flush with a surface of the semiconductor chip opposite from the solid device.
The solid device may be a wiring board or a second semiconductor chip which is different from the semiconductor chip.
In accordance with the present invention, the stiffener which may be formed of a synthetic resin is provided around the semiconductor chip, whereby the solid device can be strengthened and prevented from being warped due to thermal stress.
In some cases, a heatsink plate for dissipating heat from the semiconductor chip is provided on the surface of the semiconductor chip opposite from the solid device. Even in such a case, the heatsink plate can easily be provided in contact with the surface of the semiconductor chip opposite from the solid device and the surface of the stiffener opposite from the solid device which are generally flush with each other.
Since the surface of the semiconductor chip opposite from the solid device is generally flush with the surface of the stiffener opposite from the solid device, a production serial number and the like can be inscribed across the flush surfaces. Even if the semiconductor chip has a small size as viewed in plan, a sufficient space can be provided for the inscription.
Where a plurality of inventive semiconductor devices are mounted in a stacked relation on a mounting board, a heightwise integration density can be increased because the semiconductor devices each have a smaller thickness.
The surface of the semiconductor chip opposite from the solid device and the surface of the stiffener opposite from the solid device are preferably mirror-finished surfaces. When the semiconductor device is mounted on a mounting board under monitoring with a camera, for example, the camera can recognize the semiconductor device with an improved accuracy because diffused light reflection on the semiconductor chip and the stiffener is suppressed. Therefore, the semiconductor device can accurately be positioned at a desired mounting position on the mounting board. The mirror-finished surfaces each have an increased surface strength, so that the warp of the semiconductor device can more effectively be prevented which may otherwise occur due to thermal expansion.
The semiconductor chip may be bonded to the solid device with an active surface thereof being opposed to the solid device. In this case, the semiconductor device is fabricated through a fabrication process which, for example, includes the steps of: bonding a semiconductor chip to a surface of a solid device with an active surface of the semiconductor chip being opposed to the solid device; providing a synthetic resin material to surround the periphery of the semiconductor chip with the synthetic resin material; and simultaneously planarizing the semiconductor chip bonded to the surface of the solid device and the synthetic resin material provided around the semiconductor chip after the resin provision step, so that a surface of the semiconductor chip opposite from the active surface is generally flush with a surface of the synthetic resin material opposite from the solid device.
In this process, the semiconductor chip and the synthetic resin material (stiffener) which initially each have a relatively great thickness are first provided on the surface of the solid device, and then subjected to the planarization for thickness reduction. Therefore, there is no possibility that the semiconductor chip and the stiffener suffer from cracking and chipping, unlike a process in which a thin semiconductor chip and a thin stiffener are provided on the surface of the solid device.
Even if a polishing or grinding process with the use of a grinder or a CMP (chemical mechanical polishing) process is employed for the planarization, a stress exerted on the semiconductor chip can be alleviated by simultaneously polishing or grinding the semiconductor chip and the synthetic resin material. Therefore, the warp and chipping of the semiconductor chip can be prevented.
The semiconductor chip may be spaced from the stiffener. With this arrangement, a space provided between the semiconductor chip and the stiffener can accommodate a difference in thermal expansion between the semiconductor chip and the stiffener even if the semiconductor device is exposed to a high temperature. Therefore, the warp of the semiconductor device can more effectively be prevented which may otherwise occur due to the thermal expansion.
A low elasticity filler having a lower elasticity than the stiffener may be filled in a space defined between the surface of the solid device and the surface of the semiconductor chip opposed to the solid device. With this arrangement, the active surface of the semiconductor chip can be protected by the low elasticity filler filled in the space between the surface of the solid device and the surface of the semiconductor chip opposed to the solid device. Where the semiconductor chip is supported by bumps provided between the solid device and the semiconductor chip with the active surface thereof being opposed to the surface of the solid device, stresses exerted on the bumps can be alleviated by the low elasticity filler.
The foregoing and other objects, features and effects of the present invention will become more apparent from the following description of the preferred embodiments with reference to the attached drawings.
REFERENCES:
patent: 5477082 (1995-12-01), Buckley, III et al.
patent: 5909056 (1999-06-01), Mertol
patent: 5973389 (1999-10-01), Culnane et al.
patent: 6066512 (2000-05-01), Hashimoto
patent: 6114763 (2000-09-01), Smith
patent: 6140707 (2000-10-01)
Kasuya Yasumasa
Oka Junji
Shibata Kazutaka
Clark Sheila V.
Rader & Fishman & Grauer, PLLC
Rohm & Co., Ltd.
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