Semiconductor device and fabrication process thereof

Details Semiconductor device and fabrication process thereof Semiconductor device and fabrication process thereof

1997-09-25

1999-04-20

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257382, 257628, 257756, H01L 2702, H01L 2708

Patent

active

058959483

ABSTRACT:
A silicon layer serving as a contact plug directly connected to a diffusion layer of a MOS transistor is provided. On a surface of an N.sup.- type diffusion layer in self-alignment with a silicon nitride layer spacer and a field oxide layer, an N.sup.+ type monocrystalline silicon layer formed by anisotropic selective epitaxial growth method is directly connected. The surface of the N.sup.+ type monocrystalline silicon layer is directly connected to an N.sup.+ type monocrystalline silicon layer formed by isotropic selective epitaxial growth.

REFERENCES:
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patent: 5399890 (1995-03-01), Okada et al.
patent: 5705838 (1998-01-01), Jost et al.
patent: 5706164 (1998-01-01), Jeng
patent: 5729034 (1998-03-01), Park
patent: 5736770 (1998-04-01), Asai et al.
patent: 5780882 (1998-07-01), Sugiura et al.
H. Hada et al., "A Self-Aligned Contact Technology Using Anisotropical Selective Epitaxial Silicon For Giga-Bit DRAM", IEDM, 1995, pp. 665-668.

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