Active solid-state devices (e.g. – transistors – solid-state diode – Including region containing crystal damage
Reexamination Certificate
1998-01-06
2001-05-08
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Including region containing crystal damage
C257S155000, C257S139000, C257S341000, C257S913000, C257S172000
Reexamination Certificate
active
06229196
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and methods for manufacturing the same, and particularly to a semiconductor device having a vertical structure with reduced ON-state voltage and improved fabrication yield and a method for manufacturing the same.
2. Description of the Background Art
FIG. 43
shows the structure of an insulated-gate bipolar transistor (hereinafter, referred to as an IGBT)
90
as an example of a vertical-type semiconductor device in which the main current flows vertically with respect to the main surface of the substrate.
As shown in
FIG. 43
, the IGBT
90
has a semiconductor base body
1
composed of a P
+
collector layer
20
, an N
+
buffer layer
21
, an N
−
layer
22
laid one on top of another, a gate electrode
27
selectively formed on the upper main surface of the semiconductor base body
1
, specifically on the external main surface of the N
−
layer
22
with a gate insulating film
26
interposed therebetween, an emitter electrode
28
selectively formed on the upper main surface of the semiconductor base body
1
, and a collector electrode
29
formed on the lower main surface of the semiconductor base body
1
, specifically on the external main surface of the P
+
collector layer
20
.
A P base region
23
is selectively formed in the part extending from the surface of the N
−
layer
22
to the inside thereof, and a pair of N
+
emitter regions
24
are selectively formed to face each other at a certain interval in the part extending from the surface of the P base region
23
to the inside thereof. Formed on the facing ends of the pair of N
+
emitter regions
24
and on the P base region
23
therebetween is the emitter electrode
28
. The gate electrode
27
is located over the other ends of the pair of N
+
emitter regions
24
, the part of the P base region
23
adjacent to those ends, and the part of the N
−
layer
22
adjacent to the P base region
23
, with the gate insulating film
26
interposed therebetween. When the device operates, the part inside the surface of the P base region
23
interposed between the N
−
layer
22
and the N
+
emitter regions
24
under the gate electrode
27
serves as a channel region
25
. The P base region
23
, the N
+
emitter regions
24
, the gate insulating film
26
, the gate electrode
27
, and the emitter electrode
28
formed on the upper main surface side of the semiconductor base body
1
form an MOSFET, which part is called an MOS region
10
.
Next, operation of the IGBT
90
will be described. An application of a positive voltage to the gate electrode
27
causes the surface of the P base region
23
right under the gate electrode
27
to invert into N type to form the channel region
25
, so that the electrons are injected from the N
+
emitter regions
24
through the channel region
25
into the N
−
layer
22
. At the same time, a very large number of holes (minority carriers) are injected from the P
+
collector layer
20
into the N
−
layer
22
, so that the N
−
layer
22
causes conductivity modulation, which provides the advantage that the electric resistance of the N
−
layer
22
becomes relatively low.
In the operation of the IGBT
90
described above, the electric resistance of the N
−
layer
22
causing the conductivity modulation can be expressed by the expression (1) below:
R
∝
W
2
2
D
·
τ
2
In this expression (1), R represents the electric resistance of the N
−
layer
22
, W represents the thickness of the N
−
layer
22
, D represents the diffusion coefficient of carriers, and &tgr; represents the life time of the carriers in the N
−
layer
22
. Accordingly, the expression (
1
) shows that the electric resistance of the N
−
layer
22
is proportional to the thickness of the N
−
layer
22
and largely depends on the life time of the carriers in the N
−
layer
22
.
Increasing the breakdown voltage of the IGBT
90
requires increasing the thickness of the N
−
layer
22
, which raises the problem of high electric resistance. Suppressing the increase in electric resistance as low as possible requires lengthening the life time of the carriers. However, the life time of the carriers largely depends on the quantity of metal impurities, especially heavy metal impurities, included in the semiconductor layer.
An unprocessed, new semiconductor substrate (wafer) contains almost no heavy metal impurities. However, the semiconductor layers are inevitably contaminated with heavy metal impurities in various process steps for fabricating semiconductor devices.
The contamination by heavy metal impurities will now be described for the process of fabricating the IGBT
90
as an example. For example, to obtain a breakdown voltage equal to or higher than 2000 V with the IGBT
90
, the N
−
layer
22
must have a thickness of 150 &mgr;m or larger. With an IGBT of an intermediate breakdown voltage (e.g., a breakdown voltage of about 1200 V) or lower, an N+buffer layer and an N
−
layer are formed on a P
+
substrate generally by epitaxial growth. However, this method can be used because the N
−
layer has a small thickness, and forming an N
−
layer
22
of 150 &mgr;m or thicker by epitaxial growth is technically very difficult and very expensive at present.
Accordingly, when manufacturing the IGBT
90
, a single-crystal N
−
silicon substrate is prepared as a semiconductor substrate and N-type impurities are introduced from the back side of the N
−
silicon substrate (the side on which the collector electrode is formed) by an ion implantation, and a thermal diffusion is applied to obtain a desired diffusion depth to form the N
+
buffer layer
21
. Next, P-type impurities are introduced from the back side of the N
−
silicon substrate by an ion implantation, followed by a thermal diffusion to a desired diffusion depth to form the P
+
collector layer
20
.
Since a thermal treatment is conducted when forming the N
+
buffer layer
21
at 1200° C. for 20 hours, for example, the possibility of contamination with heavy metal impurities is stronger than the case of IGBTs with intermediate or lower breakdown voltages which do not require this kind of process step.
Obtaining semiconductor devices with long carrier life time requires prevention of the contamination by heavy metal impurities, which requires heavy equipment investment to improve the fabrication systems and the like.
Generally, however, in order to prevent the contamination by heavy metal impurities to prevent reduction in life time of carriers without requiring such equipment investment, gettering process for excluding the injurious heavy metal impurities from the semiconductor layers is adopted in the process of fabricating semiconductor devices.
Heavy metal impurities such as iron (Fe) and copper (Cu) have a property of depositing at crystal defects in silicon, and a property of presenting very large diffusion coefficients at high temperatures. The gettering utilizes these properties. Known gettering methods include the intrinsic gettering in which a crystal defect layer forming a gettering core is formed in the silicon substrate in such a part as not to affect the electric characteristics and the extrinsic gettering in which a mechanically damaged layer is formed as a gettering layer by forming crystal defects on the back side of the wafer by sandblasting or the like, or in which a polysilicon layer containing many crystal defects is formed.
In the conventional extrinsic gettering method, the gettering layer is finally removed in most cases.
For example, Japanese Patent Laying-Open Gazette No.58-138035 shows a structure in which a polysilicon layer for gettering is formed on the back side of a semiconductor substrate, which suggests removing the polysilicon layer when an electrode is formed on the back s
Shishido Nobuyasu
Takeda Mitsuyoshi
Tomomatsu Yoshifumi
Jackson, Jr. Jerome
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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