Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
2004-12-22
2008-10-07
Dang, Trung (Department: 2892)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
C257S532000, C257SE21008
Reexamination Certificate
active
07432170
ABSTRACT:
On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
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Furumiya Masayuki
Kikuta Kuniko
Nakashiba Yasutaka
Nakayama Makoto
Ohkubo Hiroaki
Dang Trung
NEC Electronics Corporation
Sughrue & Mion, PLLC
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