Semiconductor device and fabrication method thereof

Details Semiconductor device and fabrication method thereof Semiconductor device and fabrication method thereof

2001-01-24

2003-03-04

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000, C438S595000, C438S618000, C438S622000

Reexamination Certificate

active

06528404

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and in particular to a metal oxide semiconductor field effect transistor (MOSFET) device which can improve performance and reliability by restricting generation of a hot carrier effect, and a fabrication method thereof.
2. Description of the Background Art
An operational effect of a semiconductor device is improved by increasing an integration degree thereof. As the integration degree is increased, the number of chips to be fabricated on a single wafer is also increased, and thus the unit cost of the chip is decreased. Accordingly, the integration degree of the semiconductor device is continuously increased, and thus a submicron semiconductor device can be fabricated.
However, while a size of the device is gradually reduced, a voltage supplied to the device is almost constantly maintained. As the integration degree of the device is increased, an electric field formed in the device becomes stronger, which results in a hot carrier effect.
An N-channel MOSFET device will now be discussed.
The hot carrier effect influences the device characteristics, as follows.
1) The electric field of a drain junction biased in a backward direction may cause impact ionization and carrier propagation. Here, a hole which is generated represents the substrate current. Some of the holes move to the source, reduces the source barrier and causes electron injection from the source to the p-type region. Actually, in case an n-p-n transistor operation is generated among the source-channel-drain, a gate may not be able to control the current.
2) Because of the strong electric field, the electrons may travel beyond an energy barrier existing at an interface between the semiconductor substrate and a gate insulating layer, and may be injected into the gate insulating layer. The injected electrons are trapped in the gate insulating layer and cause interface states. As a result, a threshold voltage and current-voltage characteristics of the device are varied. In addition, various other problems may occur.
In order to fabricate a semiconductor device having high performance and reliability by solving performance deterioration resulting from the hot carrier effect, various MOSFET device structures have been suggested. Here, a remarkable suggestion is a MOSFET device having a lightly doped drain (LDD) structure. The LDD structure reduces the size of a peak electric field generated at a depletion region of the MOSFET device, thereby restricting generation of the hot carrier effect. In addition, a lightly doped n− region is formed between a gate edge and a source/drain region (n+ region). Accordingly, a voltage drop generated in the device occurs in a wider region, as compared with a conventional MOSFET device.
However, the LDD structure has a disadvantage in that a weak overlap occurs and thus reduces an overlapped region between the gate and the drain. The influence of the gate is decreased at a region where the weak overlap takes place. As a result, when forming a channel by applying a voltage over a threshold voltage to the gate, a channel having a high resistance is formed at the region where the weak overlap takes place, as compared with a channel corresponding to a center portion of the gate.
In order to solve the weak overlap in the LDD structure, a fully overlapped LDD structure has been suggested. The fully overlapped LDD structure positions a peak electric field in the MOSFET device below the gate, which results in improved performance and reliability of the MOSFET device. Since the peak electric field is positioned below the gate, a voltage drop between the drain and the channel when a strong voltage is supplied to the gate is minimized, a horizontal electric field is decreased, and performance deterioration of the device when a localized charge increases a resistance of the drain is prevented. Furthermore, as compared with the conventional LDD structure, the doping density of the n− region can be lowered, and thus the horizontal electric field can be decreased.
The easiest method for implementing the fully overlapped LDD structure is to form a conductive spacer consisting of a polycrystalline silicon and the like at the sides of the gate. After the formation of the gate, the conductive spacer is formed at the sidewalls of the gate by forming the n- region by ion implantation and depositing and etching the polycrystalline silicon.
FIGS.
1
(
a
) to
1
(
e
) illustrate the sequential steps of the conventional method for fabricating the semiconductor device having the fully overlapped LDD structure using the conductive spacer.
As shown in FIG.
1
(
a
), a gate insulating layer
3
, a polycrystalline silicon layer
5
and a capping insulating layer
7
are sequentially formed and stacked on a semiconductor substrate
1
.
Thereafter, as depicted in FIG.
1
(
b
), a photoresist film pattern (not shown) is formed at a predetermined region of the capping insulating layer
7
. A capping layer
17
and a gate electrode
15
are formed by employing the photoresist film pattern as a mask, and sequentially etching the capping insulating layer
7
and the polycrystalline silicon layer
5
. The capping layer
17
and the gate electrode
15
compose a gate
20
. Then, the photoresist film pattern (not shown) is removed.
As shown in FIG.
1
(
c
), ions such as As and P are implanted into the semiconductor substrate
1
at the sides of the gate
20
by using the gate
20
as a mask. Accordingly, an n− region (not shown) is formed at both sides of the gate electrode
15
.
As illustrated in FIG.
1
(
d
), a conductive polycrystalline silicon layer
9
is deposited on the whole surface of the semiconductor device as shown in FIG.
1
(
c
).
Thereafter, as depicted in FIG.
1
(
e
), the polycrystalline silicon layer
9
is removed by anisotropic etching, except for the polycrystalline silicon layer
19
at the sides of the gate
20
. Thus, a conductive spacer
19
is formed at the both sides of the gate
20
. Ions such as As and P are implanted into the semiconductor substrate
1
at the side portions of the conductive spacer
19
by using the gate
20
and the conductive spacer
19
as a mask. Accordingly, an n+ region (not shown) is formed.
FIG. 2
is an enlarged view of part A in the conventional semiconductor device having the fully overlapped LDD structure using the conductive spacer as shown in FIG.
1
(
e
). Part B in
FIG. 2
shows the damaged gate insulating layer
3
. That is, since an etching gas is concentrated on part B in the step for etching the gate electrode
15
, the gate insulating layer
3
is overetched.
Because of the damaged gate insulating layer, when the voltage is applied to the gate
20
, the electric field is concentrated on the damaged part of the gate insulating layer
3
. As a result, the hot carrier effect may easily occur, and a breakdown voltage of the device may be decreased due to deterioration of the quality of the gate insulating layer
3
.
Such disadvantages can be overcome by re-oxidizing the gate insulating layer
3
after removing the damaged part thereof. However, the re-oxidation step oxidizes the sides of the gate electrode
15
consisting of the polycrystalline silicon, in addition to the gate insulating layer. Therefore, an oxidation layer (not shown) is formed at the sides of the gate electrode
15
, and thus the gate electrode
15
and the conductive spacer
19
are electrically insulated from one another. Consequently, it is impossible to implement the fully overlapped LDD structure.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device which can improve performance and reliability by preventing a breakdown voltage from being reduced due to a damaged part of a gate insulating layer. This is accomplished by removing the damaged part of the gate insulating layer and re-oxidizing the gate insulating layer without electrically isolating the gate electrode from the

Affiliated with

Also associated with

Rating

Semiconductor device and fabrication method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and fabrication method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and fabrication method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3061231