Semiconductor device and fabrication method thereof

Details Semiconductor device and fabrication method thereof Semiconductor device and fabrication method thereof

2000-01-07

2003-04-08

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S380000, C257S381000, C257S393000

Reexamination Certificate

active

06545325

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof. Particularly, the present invention relates to a semiconductor device stabilized in the static random access memory cell operation, and a fabrication method of the same.
2. Description of the Background Art
First, the structure of a memory cell in a conventional static random access memory (represented as SRAM hereinafter) will be described. Referring to
FIG. 17
, one memory cell
107
in an SRAM includes two access transistors A
1
and A
2
, and two driver transistors D
1
and D
2
.
In the region of memory cell
107
, element formation regions
101
a
and
101
b
divided by a field oxide film are formed at the surface of a silicon substrate. Access transistor A
1
and driver transistor D
1
are formed at element formation region
101
a
. Access transistor A
2
and driver transistor D
2
are formed at element formation region
101
b
. Pluralities of such memory cells
107
are formed in one SRAM.
An example of fabricating the above memory cell will be described hereinafter according to the cross sectional line XVIII—XVIII of FIG.
17
. Referring to
FIG. 18
, a gate electrode
102
a
of access transistor A
1
is formed on a silicon substrate
110
with a gate insulation film
122
a
thereunder. Also, a gate electrode
102
b
of driver transistor D
2
is formed via a gate insulation film
122
b.
By implanting n type impurities, for example, into silicon substrate
110
with gate electrodes
102
a
and
102
b
as a mask, an n
−
drain region
103
a
and an n
−
source region
103
b
of access transistor A
1
and an n
−
drain region
103
g
of driver transistor D
1
are formed. Referring to
FIG. 19
, a TEOS film
111
is formed on silicon substrate
110
so as to cover gate electrodes
102
a
and
102
b.
Referring to
FIG. 20
, TEOS film
111
is subjected to anisotropic etching, whereby a sidewall insulation film
112
is formed at both sides of gate electrode
102
a
and both sides of gate electrode
102
b.
Referring to
FIG. 21
, n type impurities are implanted into silicon substrate
110
with sidewall insulation film
112
and gate electrodes
102
a
and
102
b
as a mask, whereby an n
+
drain region
133
a
and an n
+
source region
133
b
of access transistor A
1
and an n
+
drain region
133
g
of driver transistor D
1
are formed.
Accordingly, access transistor A
1
is formed including gate electrode
102
a
, n
−
and n
+
drain regions
103
a
and
133
a
, and n
−
and n
+
source regions
103
b
and
133
b
. At the same time, the other driver transistors D
1
and D
2
and access transistor A
2
shown in
FIG. 17
are formed. Thus, the main part of the memory cell in SRAM is formed.
As one method of stabilizing the memory cell operation in an SRAM, the method of increasing the ratio of the current drivability of the driver transistor to that of the access transistor (beta ratio) is known. More specifically, the impurity concentration of the source region in the access transistor is lowered to reduce the current drivability of the access transistor for improvement of the beta ratio.
When the above-described fabrication method is employed, an n
+
source region
133
b
of relatively high impurity concentration is formed at the source region of access transistor A
1
. Therefore, the current drivability of the access transistor cannot be reduced. As a result, the beta ratio cannot be improved.
In view of the foregoing, a structure that does not have an n
+
source region in the source region of the access transistor is employed. An example of a fabrication method of a memory cell having such a structure will be described hereinafter.
Referring to
FIG. 22
subsequent to the step of
FIG. 20
, a photoresist pattern
115
a
is formed to cover n
−
source region
103
b
of access transistor A
1
in element formation region
1
a
sandwiched by gate electrodes
102
a
and
102
b.
At the same time, a photoresist pattern
115
b
is formed to cover the n
−
source region of access transistor A
2
in element formation region
101
b
, as shown in FIG.
23
.
Referring to
FIG. 24
, n
+
type impurities are implanted into silicon substrate
110
with photoresist patterns
115
a
and
115
b
as a mask. An n
+
drain region
133
a
of access transistor A
1
and an n
+
drain region
133
g
of driver transistor D
1
are formed. It is noted that an n
+
source region is not formed in n
−
source region
103
b
here. Then, photoresist patterns
115
a
and
115
b
are removed.
Referring to
FIG. 25
, a silicon oxide film
116
is formed on silicon substrate
110
to cover gate electrodes
102
a
and
102
b
and sidewall insulation film
112
. Referring to
FIG. 26
, a predetermined photoresist pattern (not shown) is formed on silicon oxide film
116
.
By etching silicon oxide film
116
anisotropically with that photoresist pattern as a mask, a storage node contact hole
104
a
is formed, for example, that exposes the surface of gate electrode
102
a
and the surface of n
−
and n
+
source regions
103
b
and
133
b.
Referring to
FIG. 27
, a polysilicon film
114
doped with phosphorous and the like is formed in storage node contact hole
104
a
. Alternatively, an undoped polysilicon film can be formed, and then impurities such as arsenic can be implanted into that film. Polysilicon film
114
is subjected to a predetermined process, whereby an interconnection and the like are formed. Thus, the main part of a memory cell is completed.
Accordingly, a semiconductor memory device including a memory cell of a relatively high beta ratio of an SRAM is obtained. The sectional views of
FIGS. 26 and 27
correspond to the cross sectional line XXVI—XXVI of FIG.
17
.
The above fabrication method absent of an n
+
source region in the source region of the access transistor induces the following problem.
First, a photomask to form photoresist patterns
115
a
and
115
b
had to be newly added.
Second, the property of the access transistor in the memory cell varies such as increase in the contact resistance caused by misalignment of photoresist patterns
115
a
and
115
b
. This problem will be described hereinafter.
In the formation of photoresist patterns
115
a
and
115
b
, photoresist patterns
115
a
and
115
b
may be formed displaced from the predetermined position as shown in, for example,
FIGS. 28 and 29
, due to misalignment in photolithography.
In the case where photoresist pattern
115
a
is formed as shown in
FIGS. 28 and 29
, the region in the proximity of the end portion of gate electrode
102
b
is covered by photoresist pattern
115
a
. Impurities of relatively high concentration will not be implanted into this region.
Therefore, the region remaining as the n
−
source region differs from access transistor A
1
to access transistor A
2
. The resistance of the source regions may differ therebetween. As a result, the characteristics of the access transistors may become asymmetric in the memory cell.
Furthermore, in the case where only gate electrode
102
b
and n
−
source region
103
b
are exposed at the bottom of storage node contact hole
104
a
provided at this region, as shown in
FIG. 30
, the contact resistance of polysilicon film
114
and n
−
source region
103
b
will increase.
As to photoresist pattern
115
a
, the region in the proximity of the end of gate electrode
102
d
is not covered with photoresist pattern
115
b
, as shown in FIG.
28
. Impurities of relatively high concentration will be implanted into the region of this portion. Therefore, gate electrode
102
d
and n
+
source region of access transistor A
2
will be exposed at the bottom of storage node contact hole
104
b
formed at this region. As a result, the contact resistance at this region of storage node contact hole
104
b
will become relatively small.
Thus, there was a problem that the memory cell cannot op

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