Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-21
2003-01-21
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S140000, C257S401000, C257S355000
Reexamination Certificate
active
06509617
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof and, particularly, the present invention relates to a semiconductor device, which can easily utilize a plurality of power source voltages in an application processing stage with respect to a base chip of a LSI such as a gate array LSI, an embedded array LSI, a full customized LSI and easily form protective circuits against ESD (Electrostatic Discharge) and/or EOS (Electrical Over-Stress) and is programmable flexibly correspondingly to an I/O cell assignment, and a fabrication thereof.
2. Description of the Prior Art
It has been usual in a base chip of a LSI, which is virtual in a design stage before a program for forming a specific circuit, etc., is not written, that a core portion and an I/O portion are formed separately. Such base chip or a LSI fabricated on the basis of the base chip by performing an application design therefor generally has a structure shown it FIG.
5
. As shown in
FIG. 5
, which is a plan view of an example of a base chip
1
of a LSI or the LSI fabricated on the basis of the base chip
1
, various functional circuits, which are usually logic circuits, are formed in the core portion. In the I/O portion thereof, a protective circuit against ESD and/or EOS, etc., is provided in order to protect the semiconductor device against external electrical stress such as electrostatically induced voltage or over-current.
In
FIG. 5
, the base chip
1
of such as a gate array LSI, an embedded array LSI or a full customized LSI, etc., includes an I/O portion
2
formed in a periphery of the base chip
1
, the core portion
3
provided within the I/O portion
2
and a guard ring
4
of a dummy collector, which is formed between the I/O portion
2
and the core portion
3
. The dummy collector functions as a collector of a parasitic transistor formed with a substrate of transistors of a CMOS circuit, which are formed in the I/O portion
2
and the core portion
3
.
A plurality of I/O cells
5
formed in the I/O portion
2
are used in a power source circuit for a usual power source voltage such as 3V and a plurality of I/O cells
6
also formed in the I/O portion
2
and shown by hatched portions are used in another power source circuit for a 5V power source. A plurality of connector pins
7
are provided in a package or casing
9
of the LSI for external connection.
In the I/O cell portion
2
, a plurality of pads
8
are formed correspondingly to the respective I/O cells
5
. Although not shown in
FIG. 5
, a buffer amplifier of the CMOS, an input protective circuit or an output protective circuit, which is constructed with diodes, etc., and a protective circuit against ESD and/or EOS, which is constructed with diodes and capacitors, etc., are usually formed in each of the I/O cells.
In a case where a plurality of power source voltages are utilized in an application process for the base chip, that is, for example, in a case where a 5V power source is used in addition to a usual 3V power source, the I/O cells
6
are selected from the I/O cells
5
as I/O cells for the 5V power source. The LSI using such base chip may be a LSI including an analog signal processor, which is operable with a power source of 5V. In a circuit including a DSP (Digital Signal Processor), the DSP is operated with a power source voltage of about 1.8V.
Incidentally, the guard ring
4
of the dummy collector is provided between the I/O portion
2
and the core portion
3
to separate the former from the latter. It is usual that the guard ring
4
corresponds to a single power source and is connected to a power source line from the single power source to form a protective circuit against ESD and/or EOS. Therefore, it is possible to utilize the guard line as a protective circuit for one power source line. However, when a plurality of different power source voltages are to be utilized, it is necessary to separately provide a corresponding number of protective circuits against ESD and/or EOS to the number of the different voltages in corner portions or a dead space of the I/O portion
2
of the base chip.
Each such protective circuit is formed in the I/O cell
6
of the I/O portion
2
. When a 3V power source is mainly used, the I/O cell
6
is usually utilized for a voltage higher than 3V, for example, 5V. Assuming that a region
3
a
of the core portion
3
is an area of a circuit operable with a 3V power source, a circuit operable with a 5V power source is formed in a region
3
b
thereof. An area of the region
3
b
is usually about 10% of the whole area of the LSI.
In the base chip of the LSI, which has the above mentioned structure, the respective I/O cells correspond to the connector pints of the package, respectively. Therefore, if a corner portion or a dead space of the base chip
1
is utilized for the I/O cells, positions of the pins
7
in the package used are limited.
That is, since it is general that the power source pins corresponding to different power source voltages are predominantly selected, the I/O cells
6
utilizing the corner portion or the dead space have to be connected by means of a lead wiring independent from the selected power source pins
7
. In such case, when the power source voltage is high, the number of protective elements or the area of the protective element must be increased correspondingly to the power source voltage.
Therefore, it becomes necessary to perform a wiring design, a pin assignment and a selection of I/O cell for every application, resulting in that the number of fabrication steps of a practical LSI is increased.
In order to solve this problem, it has been usual that a plurality of ring-like power source lines and a plurality of ring-like ground lines are provided in the I/O portion
2
correspondingly to a plurality of power source voltages and the protective circuits against ESD and/or EOS formed in the respective I/O cells are connected between the respective power source lines and the ground lines. In such case, however, a line width of each power source line is reduced, resulting in another problem that an enough number of protective elements of the power source system can not be arranged correspondingly to the power source voltages.
In order to solve the above problem, JP H12-208706A assigned to the assignee of this application discloses a technique in which wide power supply line and wide ground line are provided in parallel in an I/O portion and a core portion, respectively, and protective circuits against ESD and/or EOS are formed in the I/O portion and the core portion, respectively.
In such case, however, an area of the core portion is limited and it is necessary to perform a layout design for every one of different power source systems. With such scheme, the number of fabrication steps in a stage of application processing is increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device, which is suitable for a formation of a circuit corresponding to an application utilizing a plurality of power source voltages, is programmable flexibly correspondingly to an I/O cell assignment and can be protected against ESD and/or EOS.
Another object of the present invention is to provide a fabrication method of a semiconductor device, which can easily utilize a plurality of power source voltages in an application processing stage and is programmable flexibly correspondingly to an I/O cell assignment and can be protected against ESD and/or EOS.
In order to achieve the above objects, a semiconductor device according to the present invention includes an I/O region having a plurality of I/O cells, a core region surrounded by the I/O region and having various functional circuits and a guard ring provided between the I/O region and the core region. The guard ring is composed of a first guard ring having conductivity of one of P and N types and a second guard ring having conductivity of the other of P and N types and formed adjacent to the first guard ring. The first gua
Le Thao
Mattingly Stanger & Malur, P.C.
Nelms David
Rohm & Co., Ltd.
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