Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-09-01
2001-07-03
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S703000
Reexamination Certificate
active
06255218
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device having a conductive region formed to be in contact with an isolation insulator and an interconnection film contacted with the conductive region through an interlayer insulating film.
2. Description of the Prior Art
Typically, a semiconductor device has a diffusion region formed in an active region of a semiconductor substrate. The diffusion region is opposite in conductivity type to the substrate. The active region is defined by an isolation insulator formed selectively in the surface area of the substrate. An interlayer insulating film is formed to cover the diffusion region. An interconnection or wiring film having a contact hole is formed in the interlayer insulating film. The interconnection film is contacted with the underlying diffusion region through the contact hole to thereby realize electrical interconnection between the interconnection film and the diffusion region.
Conventionally, in the design process of the semiconductor device, the mask alignment for the above contact structure has been so determined that the contact hole is surely located on the diffusion region by giving sufficient values to the alignment margins.
Recently, with the decreasing dimension caused by progress in microfabrication technology, the integration level of the semiconductor devices on the substrate has been becoming higher and higher. To cope with this tendency, it has become indispensable for the mask alignment margins to decrease to a level as small as possible.
However, the decrease of the mask alignment margins causes various problems and as a result, it is essential to improve the contact structure and to develop fabrication processes realizing the improved structure.
Although a large number of semiconductor devices are produced and integrated on the semiconductor substrate, only one of the devices is explained in this specification for the sake of simplification of description.
FIGS. 1A
to
1
D show a first example of the conventional fabrication methods of a semiconductor device, respectively.
First, a pad oxide (SiO
2
) film
102
is formed on a surface of a p-silicon substrate
101
. A silicon nitride (Si
3
N
4
) film
103
is formed on the film
102
, and is patterned to have a specified plan shape. Using this patterned film
103
as a mask, an p-type dopant is selectively ion-implanted into the substrate
101
to form a channel stop region
104
.
Then, using this patterned silicon nitride film
103
as a mask, the surface of the substrate
101
is selectively oxidized by a thermal oxidation process, thereby producing a field oxide film
105
serving as an isolation insulator for defining active regions. The field oxide film
105
constitutes an isolation region. The state at this stage is shown in FIG.
1
A.
Subsequently, the silicon nitride film
103
and the pad oxide film
102
are removed and then as shown in
FIG. 1B
, a gate oxide film
106
for a metal-oxide-semiconductor field-effect transistor (MOSFET) is selectively formed on the surface of the active region. A gate electrode
107
a
for the MOSFET is selectively formed on the gate oxide film
106
.
Using the field oxide film
105
and the gate electrode
107
a
as a mask, an n-type dopant is ion-implanted into the substrate
101
and is followed by an annealing process, thereby producing an n-diffusion region
108
in the active region, as shown in FIG.
1
B. This region
108
serves as a source/drain region of the MOSFET.
Further, an interlayer insulating film
109
is deposited to cover the active region and the field oxide film
105
over the entire substrate
101
. A patterned resist film
110
with a penetrating window
111
is formed on the interlayer insulating film
109
, as shown in FIG.
1
C.
Using the patterned resist film
110
as a mask, the underlying interlayer insulating film
109
is selectively etched. Thus, a contact hole
112
exposing the surface of the substrate
101
is produced in the film
109
, as shown in FIG.
1
D. The resist film
110
is then removed.
Finally, as shown in
FIGS. 2 and 3
, an aluminum (Al) alloy film
113
is formed on the interlayer insulator film
109
. The film
113
is then patterned to thereby produce an interconnection or wiring film. The interconnection film
113
is contacted with the underlying n-type diffusion region
108
through the contact hole
112
.
If the mask alignment error exceeds the specified alignment margin during the process of forming the contact hole
112
, the opposing edge of the field oxide film
105
to the diffusion region (source/drain region)
108
is also etched, as shown in FIG.
1
D. As a result, the interconnection film
113
is contacted with the substrate
101
itself at a position
129
outside the diffusion region
108
. This means that the interconnection film
113
and the substrate
101
are in short-circuit.
A similar problem to the above occurs in a semiconductor device with the trench isolation structure. Although various types of the trench isolation structures have been developed, only one of them is shown here.
FIGS. 4A
to
4
I show a second example of the conventional fabrication methods of a semiconductor device, respectively, which was disclosed in IEDM Technical Digest, pp57-60, 1993.
First, a pad oxide film
202
is formed on a surface of a p-silicon substrate
201
. A silicon nitride film
203
is then formed on the film
202
. Using a masking film (not shown), the surface area of the substrate
201
is selectively etched together with the films
202
and
203
, thereby producing a trench
214
having a specified plan shape and a specified depth in the substrate
201
.
Next, as shown in
FIG. 4B
, a silicon oxide film
215
is formed on the inner surface of the trench
214
by a thermal oxidation process. Boron is selectively ion-implanted into the substrate
201
through the film
215
, thereby forming a p-type ion-implantation region
216
.
A silicon dioxide film
217
is deposited on the silicon nitride film
203
and in the trench
217
. The film
217
is then removed except for the inside of the trench
214
by a planarization process such as a chemical mechanical polishing (CMP) process. Thus, the trench
214
is filled with the remaining dioxide film
217
. At the same time, the surfaces of the films
203
and
217
are planarized, as shown in FIG.
4
C.
Thereafter, the silicon nitride film
203
is removed. At this stage, the top of the silicon dioxide film
217
becomes higher than the pad oxide film
202
. A pair of sidewall spacers
228
made of silicon dioxide are formed on the film
202
at each side of the film
217
, as shown in FIG.
4
D.
The remaining pad oxide film
202
and the pair of sidewall spacers
228
are selectively removed by a wet etching process, thereby producing an isolation insulator made of the buried silicon dioxide film
217
in the trench
214
, as shown in FIG.
4
E. The isolation insulator defines an active region.
Subsequently, as shown in
FIG. 4F
, the implanted boron ions are annealed to thereby form a channel stop region
204
below the trench
214
. The region
204
surrounds the bottom and side faces of the trench
214
. Then, a gate oxide film
206
for a MOSFET is selectively formed on the surface of the active region. A gate electrode
207
a
for the MOSFET is selectively formed on the gate oxide film
206
.
Using the isolation oxide film
217
and the gate electrode
207
a
as a mask, an n-type dopant is ion-implanted into the substrate
201
, thereby producing an n-diffusion region
208
in the active region, as shown in FIG.
4
F. This region
208
serves as a source/drain region of the MOSFET.
Further, an interlayer insulating film
209
is deposited to cover the active region and the isolation oxide film
217
over the entire substrate
201
. A patterned resist film
210
with a penetrating window
211
is formed on the interlayer insulating film
209
, as shown in FIG.
4
G.
Using the patterned resist fi
Deo Duy-Vu
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Utech Benjamin L.
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