Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
2000-02-25
2002-04-16
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S736000, C257S775000, C257S435000, C257S760000
Reexamination Certificate
active
06373134
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a surface on which interconnection wiring passes over a vertical step.
Semiconductor devices are generally fabricated in the surface layers of a semiconductor wafer. Interconnection wiring is formed by coating the entire surface of the wafer with a thin metal film, then etching the film to remove unwanted metal, leaving the desired wiring pattern.
A problem in this process is that the wafer surface is generally not flat; the interconnection pattern may have to cross one or more vertical steps. At the bottom of each vertical step, there tends to be a small gap between the wafer surface and the deposited metal film. When the film is etched, the etchant can easily enter the gap and etch the metal from underneath, enlarging the gap into a sizeable tunnel that greatly reduces the thickness of the film on the vertical face of the step. Combined with subsequent joule heating or electromigration, such tunnels can create open circuits in the interconnection pattern, leading to device failure.
The thickness of the metal film on the vertical face of a step, or the ratio of this thickness to the thickness of the metal film on flat horizontal parts of the surface, is generally referred to as the step coverage.
One solution to the step-coverage problem is to increase the width of the interconnection wiring pattern wherever there is a vertical step. If the pattern is made wide enough, etchant tunneling under an interconnecting wire from the edges will be unable to reach the central part of the wire, which will remain intact. This solution is unsatisfactory, however, because wide interconnection patterns are incompatible e with high integration density.
SUMMARY OF THE INVENTION
An object of the present invention is to enable interconnection patterns to cross vertical steps without risk of electrical discontinuity, and without increasing the pattern width.
A semiconductor device according to the present invention has an electrode formation surface with a vertical step including at least one horizontal side-step. An interconnection pattern is formed on the electrode formation surface, crossing the vertical step, entirely covering the horizontal side-step.
The horizontal side-step reduces the risk of electrical discontinuity in the interconnection pattern by increasing the total length of the part of the vertical step crossed by the interconnection pattern. This increase is accomplished without an increase in the width of the interconnection pattern itself.
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Akin Gump Strauss Hauer & Feld L.L.P.
Clark Jhihan B
Oki Data Corporation
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