Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-07-06
2002-04-23
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S145000, C365S149000
Reexamination Certificate
active
06377494
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device in which data is stored by charging capacitors, and to an electronic device including the semiconductor device.
2. Description of the Related Art
A DRAM is a memory that requires periodic refreshing, and used for the memory of cellular phones, for example.
FIG. 8
is a circuit block diagram showing a part of a conventional DRAM. The configuration and operation of the conventional DRAM is described below briefly using FIG.
8
.
A DRAM comprises a memory cell array
5000
, sense amplifiers
6000
, and read/write circuits
7000
. The memory cell array
5000
comprises a plurality of memory cells MC arranged in a row-and-column configuration, a plurality of word lines WL, and a plurality of pairs of bit lines (BL and XBL). In this figure, memory cells MC
1
to MC
6
, word lines WL
1
to WL
3
, and bit lines (BL
1
and XBL
1
) and (BL
2
and XBL
2
) are shown. Each memory cell MC comprises an n-type access transistor nATr and a capacitor C for storing data. Each pair of bit lines (BL and XBL) are connected to the corresponding sense amplifier
6000
and read/write circuit
7000
.
The operation of the conventional DRAM is described taking the case of the memory cell MC
2
. First, the data write operation is described. The word line WL
1
is brought to a positive potential to turn on an access transistor nATr
2
. The bit line BL
2
is then brought to a predetermined potential. The predetermined potential is a power supply potential Vcc applied when data “H” is written to the capacitor C
2
, or a ground potential GND applied when data “L” is written to the capacitor C
2
. Data “H” or “L” is stored in the capacitor C
2
in this manner. The potential of the word line WL
1
is then brought to the ground potential GND, whereby the data on the capacitor C
2
is preserved.
Next, the data read operation is described. The bit lines BL
2
and XBL
2
are respectively brought to half the power supply potential (½) Vcc (precharging of the bit lines BL
2
and XBL
2
). The bit lines BL
2
and XBL
2
are then separated from the power supply and floated. The word line WL
1
is thereafter brought to a positive potential to turn on the access transistor nATr
2
. Consequently, the potential of the bit line BL
2
slightly rises (as much as &agr;) from (½) Vcc when data “H” has been written to the capacitor C
2
. On the other hand, the potential lowers slightly (as much as &agr;) from (½) Vcc when data “L” has been written to the capacitor C
2
.
The potential of the bit line XBL
2
, (½) Vcc, and that of the bit line BL
2
are compared and amplified by the sense amplifier
6000
. When the data of the capacitor C
2
is “H”, the potential of the bit line BL
2
becomes Vcc and that of the bit line XBL
2
becomes GND. When the data of the capacitor C
2
is “L”, on the other hand, the potential of the bit line BL
2
becomes GND and that of the bit line XBL
2
becomes Vcc. Here data reading from the memory cell MC
2
is completed. Although the data stored on the capacitor C
2
is destroyed by reading, the data is rewritten to the capacitor C
2
with the potential of the bit line BL
2
when the data has been read.
In a DRAM, when data “H” is stored in the capacitors, the data “H” changed to data “L” even while power is on if left as is. To prevent this, a DRAM requires refreshing. The refreshing period should be as long as possible in order to reduce the power consumption of a DRAM.
The change from data “H” to “L” described above is accelerated by various causes. This is described using FIG.
9
.
FIG. 9
is a circuit diagram of part of a conventional DRAM, showing the same configuration as in FIG.
8
. It is assumed that data “L” is stored in the capacitor C
2
of the memory cell MC
2
and data “H” in the capacitor C
6
of the memory cell MC
6
. When data is read from the memory cell MC
2
, the word line WL
1
is at a positive potential, the word lines WL
2
and WL
3
are at the ground potential GND, the bit line BL
2
goes to the ground potential GND, and the bit line XBL
2
goes to the power supply potential Vcc. In this case, a very small amount of electric charge Q flows from the capacitor C
6
of the memory cell MC
6
as shown by the arrow (this is referred to as a subthreshold leak current of transistor), and hence the decay from data “H” to “L” in the capacitor C
6
is accelerated.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device of which the power consumption can be reduced and an electronic device using the semiconductor device.
(1) The present invention provides a semiconductor device having a memory cell array comprising a plurality of memory cells and a plurality of word lines and in which the selection and non-selection of the memory cells is controlled by changing a potential of the word lines, wherein:
each of the memory cells comprises an n-type access transistor and a capacitor having a cell plate;
predetermined potential is applied to the cell plate,
a potential of the cell plate during a period when the memory cells are selected is a first potential;
a potential of the cell plate during a period when the memory cells are non-selected is a second potential larger than the first potential; and
a switching of the potential of the cell plates is controlled by changing a potential of the word lines.
In the present invention, the potential of the cell plates during a non-selected period of the memory cells (second potential) is greater than that of the cell plates during a selected period of the memory cells (first potential). By this configuration, the potential of the nodes (drains) of the n-type access transistors connected to the capacitors is raised because of capacitance coupling by the capacitors during a non-selected period. The rise in the potential of the nodes makes it possible to increase the margin of data “H” decision level in the capacitors. According to the present invention, the refreshing period therefore can be extended and, consequently, the power consumption can be reduced.
(2) In the present invention,
the semiconductor device may have a plurality of memory cell groups each of which includes a plurality of the memory cells;
the n-type access transistor included in one of the memory cell groups may be controlled by one of the word lines;
the cell plates at the n-type access transistors included in each of the memory cell groups may be connected together; and
the cell plates of one of the memory cell groups may be separated from the other cell plates in a rest of the memory cell groups.
(3) In the present invention, a potential of the cell plate may be switched for each of the memory cell groups.
In this configuration, the potential switching speed of the cell plates can be increased in comparison with the case in which all capacitors of the entire memory cell array are connected together. Moreover, since the capacitance of the cell plates in which the potential is changed is decreased in this embodiment, the power consumption of the semiconductor device can be reduced.
(4) In the present invention, the semiconductor device may have a cell-plate-potential-switching circuit that includes the word lines, a plurality of n-type switch transistors and a plurality of p-type switch transistors, and
in one of the word lines, and one of the n-type switch transistors and one of the p-type switch transistors provided to the one of the word lines,
the one word line may be connected to a gate electrode of the one n-type switch transistor and a gate electrode of the one p-type switch transistor;
one of sources/drains of the one n-type switch transistor may be connected to the cell plate provided to one of the memory cell groups corresponding to the one word line;
the first potential may be applied to another one of the sources/drains of the ore n-type switch transistor;
one of sources/drains of the one p-type switch transistor may be connected to the cell plate provided to one of the memory cell groups corres
Ho Hoai V.
Hogan & Hartson L.L.P.
Seiko Epson Corporation
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