Semiconductor device, and design method, inspection method,...

Details Semiconductor device, and design method, inspection method,... Semiconductor device, and design method, inspection method,...

2011-04-12

2011-04-12

Nguyen, Ha Tran T (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

07924042

ABSTRACT:
A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit blocks wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and the measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, which is formed in any layer of the semiconductor device; planar-arranging the measurement terminals and the circuit blocks; and establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

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