Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2001-06-15
2002-12-10
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S185040, C365S189070
Reexamination Certificate
active
06493278
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority to Japanese Patent Application Number 2000-180627 filed Jun. 15, 2000, the content of which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a memory space composed of rewritable semiconductor memory cells, and a control device for use therewith. In particular, the present invention relates to a semiconductor device having a security function for protecting from unauthorized access any content which is stored in the memory space, and a control device for use therewith.
2. Description of the Related Art
A semiconductor device such as a semiconductor memory device has a memory space composed of rewritable semiconductor memory cells which are represented by respective addresses. A semiconductor memory device may store information (such as copyright-protected subject matter or privacy information of individuals) which should not be subjected to unauthorized reading by a third party, or information which should not be subjected to unauthorized overwriting (as in the case of IC card applications). There have been proposed some semiconductor devices having a memory space, and control devices for use therewith, which have a security function for protecting the stored contents (data) from such unauthorized access.
Hereinafter, a conventional semiconductor device having a security function will be described with reference to
FIGS. 5
to
7
.
FIG. 5
is a schematic block diagram illustrating a minimum structure for realizing a security function. A semiconductor device
600
shown in
FIG. 5
includes a memory accessing means
604
, a memory
613
having a memory space (semiconductor memory cells) for storing data, and a security means
609
inserted therebetween. With the security means
609
, it is possible to restrict some or all of the operations which are externally requested.
The memory accessing means
604
externally receives an address signal
601
, a control signal
602
, and a data signal
603
, and outputs an address signal
605
which designates one or several of the storage units (semiconductor memory cells) in the memory space of the memory
613
to which access is to be made; a control signal
607
which designates the type and/or content of access to be performed to the memory
613
; and a data signal
608
which is used for inputting or outputting of data in accordance with the designated content in the memory
613
.
The security means
609
is capable of restricting some or all of the operations which are represented by a signal which is output from the memory accessing means
604
to the memory
613
. For example, the security means
609
is capable of restricting the reading of any content which is stored in the memory
613
, restricting the overwriting of any content which is stored in the memory
613
, or both.
A given operation which is instructed by the memory accessing means
604
to be per formed on the memory
613
is represented by the address signal
605
, the control signal
607
, and the data signal
608
which are output to the security means
609
. In the case where the content of the operation which is instructed by the memory accessing means
604
to be performed on the memory
613
is permitted, the security means
609
outputs an address signal
610
, a control signal
611
, and a data signal
612
to the memory
613
to perform an operation as instructed by the memory accessing means
604
. On the other hand, in the case where the content of the operation which is instructed by the memory accessing means
604
to be performed on the memory
613
is not permitted, the security means
609
applies a conversion process to at least one of the address signal
610
, the control signal
611
, and the data signal
612
. If the externally instructed operation involves outputting of the data which is stored in the memory
613
, the security means
609
applies a conversion process to the data signal
608
which is output from the security means
609
to the memory accessing means
604
. Thus, the operations to the memory
613
are restricted so that any operations which are not permitted will not occur, thereby realizing a security function for the memory
613
.
All of the component elements of the semiconductor device
600
shown in
FIG. 5
may be provided on one device. Alternatively, the component elements may be distributed over a number of devices so that a security function will be realized when the devices are used in combination. For example, in the case where the security function is to be realized on a single device, an interface circuit for interfacing with the exterior of the device may be utilized as the memory accessing means
604
, while a circuit for restricting some or all of the operations which require access to the memory space may be inserted (as the security means
609
) between the memory
613
as a circuit having a memory space and the memory accessing means
604
.
Alternatively, in the case where the security function is to be realized on a number of devices collectively, e.g., when the memory accessing means
604
, the security means
609
, and the memory
613
are all provided on discrete devices, a circuit for restricting some or all of the operations which require access to the memory space may be inserted (as the security means
609
) between a memory controller functioning as the memory accessing means
604
and the memory
613
having a memory space.
Hereinafter, a semiconductor device which is capable of outputting dummy data when a read access to the memory is made will be specifically described, by an illustration of a structure in which read operations to a memory are restricted until deactivation of a security function.
FIG. 6
is a schematic block diagram illustrating a conventional semiconductor device
450
which realizes the above-described security function. The semiconductor device
450
includes an interface circuit
404
, a security circuit
409
, and a memory
413
having a memory space composed of semiconductor memory cells. The security circuit
409
includes a password storage circuit
414
for storing a password, a comparison circuit
416
, and an operation restriction circuit
418
for restricting operations to be performed on the memory
413
.
In accordance with the semiconductor device
450
, restriction on read operations is established (i.e., a security function is set) at the time when the semiconductor device
450
is turned ON. The security function can only be deactivated if a password (security control signal)
407
which is externally input via the interface circuit
404
matches a fixed password which is stored in the password storage circuit
414
in the security circuit
409
, after which read operations can be performed normally.
In the case of making an external access to the stored content (data) which is stored in a given address in the memory
413
of the semiconductor device
450
, an address signal
401
, a control signal
402
, and a data signal
403
are input to the interface circuit
404
. The interface circuit
404
outputs an internal address signal
405
and an internal control signal
406
, and if necessary an internal data signal
408
, to the memory
413
. In the case where the security function of the memory
413
is deactivated, the operation restriction circuit
418
outputs an address signal
410
, a control signal
411
, and a data signal
412
to the memory
413
in accordance with the address signal
401
, the control signal
402
, and the data signal
403
, which are externally supplied (or more directly, in accordance with the internal address signal
405
, the internal control signal
406
, and the internal data signal
408
). As a result, a normal operation is performed.
The semiconductor device
450
is constructed in such a manner that the security function of the memory
413
is set in an initial state which follows after the semiconductor device
450
is turned ON. As a re
Sumitani Ken
Takata Hidekazu
Auduong Gene N.
Ho Hoai
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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