Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-27
2004-08-17
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S285000, C257S286000, C257S287000, C257S335000, C257S333000, C257S334000
Reexamination Certificate
active
06777728
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
The present application is based on Japanese priority application No. 2001-399595 filed on Dec. 28, 2001, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly to a high-speed semiconductor device having enhanced hole mobility.
2. Description of the Related Art
Si crystal-based semiconductor devices are widely used for a variety of purposes ranging from a high-speed logic element to a memory device. Focusing particularly on very high-speed logic elements, conventionally, the very high-speed logic elements are formed mainly of a compound semiconductor using a compound having small electron effective mass and high electron mobility, such as GaAs, since electron and hole mobility are limited in Si single crystals.
However, it is difficult to integrate a GaAs-based semiconductor device with a Si-based semiconductor device, and the carrier is limited to electrons, thus making it impossible to form a complementary semiconductor device using p-channel and n-channel elements.
Meanwhile, recently, very high-speed semiconductor devices boasting enhanced electron mobility have been realized with strained Si single crystals. Those Si crystal-based very high-speed semiconductor devices operate at higher speeds than the compound semiconductors.
With respect to those very high-speed semiconductor devices, there is a demand for forming a complementary semiconductor device, such as a CMOS (complementary metal oxide semiconductor) circuit, using p-channel and n-channel elements. Conventionally, however, hole mobility is prevented from being improved sufficiently in the p-channel element although electron mobility is greatly improved in the n-channel element by introducing the strain. Therefore, it is difficult to realize such a complementary semiconductor device particularly in the form of a high-density integrated circuit.
FIG. 1
is a diagram showing a valence band structure in Si crystal.
According to
FIG. 1
, the valence band of Si crystal includes a light-hole (LH) band and a heavy-hole (HH) band. In Si crystal, the ground states of those bands are degenerated. Therefore, in a semiconductor device using such Si crystal as a channel and holes as carriers, holes on the LH band are easily scattered to the HH band or the reverse scattering occurs, so that hole mobility is limited. As a result, the operation speed of the semiconductor device is also limited, thus making it difficult to realize very high-speed operation using Si crystal as a channel.
On the other hand,
FIG. 2
is a diagram showing a band structure in SiGe mixed crystal compressed isotropically in an in-plane direction.
FIG. 2
shows that by using SiGe mixed crystal, the LH band turns sharply at its ground part so that the hole effective mass m* defined by the following equation is reduced.
m
*
=
ℏ
2
d
2
ϵ
/
dk
2
Accordingly, hole mobility on the LH band is increased compared with the case of Si crystal of FIG.
1
.
The band structure of
FIG. 2
shows that the degeneration between the LH band and the HH band is canceled by applying two-dimensional isotropic compressive stress to the SiGe mixed crystal, and that the HH band is located above the LH band, that is, on the lower energy side. Accordingly, in such a band structure, the holes of the valence band exit mainly on the low-energy HH band so as to suppress hole scattering between those two bands. However, since the hole effective mass is great on the HH band, there is a limit to the desired improvement in hole mobility and to an increase in the operation speed of a p-channel MOS transistor using holes as carriers.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device in which the foregoing disadvantage is eliminated.
A more specific object of the present invention is to maximize hole mobility in a semiconductor device using holes as carriers.
Another more specific object of the present invention is, in a complementary semiconductor device including a p-channel device using holes as carriers and an n-channel device using electrons as carriers, to maximize hole mobility in the p-channel device by using strained SiGe crystal as a channel region.
Yet another more specific object of the present invention is, in a complementary semiconductor device including a p-channel device using holes as carriers and an n-channel device using electrons as carriers, to maximize hole mobility in the p-channel device by using strained SiGe crystal as a channel region and to simultaneously maximize electron mobility in the n-channel device.
The above objects of the present invention are achieved by a semiconductor device including a channel layer, a gate electrode formed on the channel layer, a p-type source region formed on a first side of the channel layer, and a p-type drain region formed on a second side of the channel layer, wherein a heavy-hole band and a light-hole band are separated by compressive strain applied isotropically in an in-plane direction in the channel layer, and a channel direction connecting said p-type source and drain regions is set substantially to a direction to maximize hole mobility in the channel layer.
According to the present invention, in a semiconductor device in which a heavy-hole band and a light-hole band are separated in a channel layer by the effect of compressive stress applied thereto isotropically in an in-plane direction, hole mobility in the channel layer can be maximized by setting the channel direction in which holes are transported preferably to around <100> instead of conventional <110>. Thereby, the operation speed of the p-channel field effect transistor (FET) can be maximized.
The above objects of the present invention are also achieved by a complementary semiconductor device including a Si substrate whose main surface is substantially a (001) crystal surface, a p-channel field-effect transistor (FET) formed in a first region of the Si substrate, and an n-channel field-effect transistor (FET) formed in a second region of the Si substrate, wherein the p-channel FET includes: a p-channel region formed of a mixed crystal layer including at least Si and Ge and storing compressive strain, the mixed crystal layer grown epitaxially in the first region on the Si substrate; a first gate electrode formed on the p-channel region; a p-type first diffusion region formed on a first side of the p-channel region; and a p-type second diffusion region formed on a second side of the p-channel region; the n-channel FET includes: an n-channel region formed of a Si layer grown epitaxially in the second region on the Si substrate; a second gate electrode formed on the n-channel region; an n-type third diffusion region formed on a first side of the n-channel region; and an n-type fourth diffusion region formed on a second side of the n-channel region; and a channel direction connecting the first and second diffusion regions is set to a direction deviating from a <110> direction in the p-channel FET.
According to the present invention, by forming a p-channel FET and an n-channel FET on a common Si substrate in a direction to particularly maximize the hole mobility of the p-channel FET, that is, by forming the p-channel and n-channel FETs in different directions, the hole mobility, or the operation speed, of the p-channel FET is maximized, while the electron mobility, or the operation speed, of the n-channel FET is prevented from being reduced. In such a complementary semiconductor device, the difference between the hole mobility of the p-channel and the electron mobility of the n-channel FETs can be reduced, so that the two transistors can be formed in a simple rectangular device region, which is advantageous in terms of integration. Therefore, the integration density of a semiconductor integrated circuit can be increased.
REFERENCES:
patent: 4862228 (198
Nakamura Shunji
Sakuma Yoshiki
Shima Masashi
Ueno Tetsuji
Erdem Fazli
Flynn Nathan J.
Fujitsu Limited
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