Semiconductor device and CMOS transistor

Details Semiconductor device and CMOS transistor Semiconductor device and CMOS transistor

2001-07-20

2004-08-10

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S413000

Reexamination Certificate

active

06774442

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device and a method for manufacturing the same, and more specifically, to a gate electrode structure and a wiring structure having the same shape as a gate electrode of MISFETs (metal insulator semiconductor field effect transistors).
2. Description of the Background Art
Either of conductive silicon single layer structure (e.g., poly-Si) and silicide/conductive silicon stacked structure (e.g., WSi
2
/poly-Si and CoSi
2
/poly-Si) has mainly been adopted for a conventional gate electrode and wiring.
However, in situations where MISFETs mid wirings are miniaturized as high integration of semiconductor integrated circuits proceeds, if the above-mentioned structures remain unchanged, the resistance value of a gate electrode and wiring is increased. The result is that the amount of signal delay in the gate electrode and wiring is increased, thereby diminishing the merit of high speed operation owing to miniaturization.
For instance, in case of CoSi
2
/poly-Si stacked structure, the sheet resistance of CoSi
2
is relatively low, namely about 7 &OHgr;, which in some cases may not be so large demerit over signal delay. However, since the CoSi
2
/poly-Si stacked structure is formed by salicide (self aligned silicide) method, it is difficult to form a SAC (self aligned contact) structure while employing the CoSi
2
/poly-Si stacked structure.
As used herein, the term “SAC structure” indicates the structure in which an insulting film such as a silicon nitride film is formed on the upper and side surfaces of a gate electrode and wiring. This insulating film functions to prevent the gate electrode and contact holes from being short-circuited even if alignment deviates when contact holes toward source/drain regions are formed in an interlayer insulating film. As high integration is advanced, the margin of the distance between the gate electrode and the contact holes toward the source/drain regions is reduced and thus liable to cause short-circuit. Hence, the SAC structure is becoming increasingly essential to high integrated semiconductor devices.
Since in salicide method a gate electrode and source/drain regions are simultaneously subjected to silicidation, an insulating film of SAC structure cannot be formed prior to salicide method. Therefore, the insulating film of SAC structure should be formed after passing through the process with salicide method.
In this state, it is however difficult to form an insulating film on the upper and side surfaces of the gate electrode. If an insulating film is formed by using photolithography and etching techniques, in some cases, alignment of the insulating film itself may deviate and fail to prevent short-circuit between the gate electrode and contact holes. For this reason, it is difficult to form the SAC structure while employing the CoSi
2
/poly-Si stacked structure.
It an also be considered to form the CoSi
2
/poly-Si stacked structure by polycide method in place of salicide method. However, the CoSi
2
/poly-Si stacked structure cannot be formed by polycide method because any suitable method for patterning the CoSi
2
/poly-Si stacked structure has not presently been discovered.
As a gate electrode structure and a wiring structure, there has been proposed a polymetal gate electrode having a metal/barrier film/conductive silicon stacked structure that can further reduce sheet resistance than the conductive silicon single layer structure or silicide/conductive silicon stacked structure and also can form the SAC structure. Such gate electrode structure and wiring structure are introduced in, e.g., “A Novel 0.15 &mgr;m CMOS Technology using W/WN
x
/Polysilicon Gate Electrode and Ti Silicided Source/Drain Diffusions” IEDM '96, pp. 455-458, and “Formation mechanism of ultrathin WSiN barrier layer in a W/WN
x
/Si system” Applied Surface Science 117/118 (1997), pp. 312-316.
FIG. 12
illustrates a polymetal gate electrode structure. In
FIG. 12
, a polymetal gate electrode is formed via a gate insulating film
2
(e.g., oxide film) oil a semiconductor substrate
1
(e.g., silicon substrate). The polymetal gate electrode has such a structure that a conductive silicon film
3
(e.g., poly-Si film), a barrier film
5
(e.g., WN
x
film or WSiN film) and a metal film
6
(e.g., W film) are stacked over the semiconductor substrate
1
in the order named.
In the polymetal gate electrode, sheet resistance is extremely small, namely about 5 &OHgr; or below, thereby to minimize the amount of signal delay in the gate electrode and wiring. This makes it possible to sufficiently utilize the merit of high speed operation owing to miniaturization.
In addition, the SAC structure can be formed easily because no formation process such as salicide method is employed. Referring to
FIG. 12
, before the conductive silicon film
3
, barrier film
5
and metal film
6
are formed into the gate electrode and wiring, an insulating film (not shown) is further patterned on the metal film
6
and then shaped into a gate electrode and wiring by using photolithography and etching techniques. This results in the gate electrode and wiring having the insulating film on the upper surface thereof. Subsequently, the usual side wall formation process is carried out to obtain the SAC structure.
The reason why the barrier film
5
is used in the polymetal gate electrode structure is as follows.
In the case of a simple two-layer stacked structure such as of metal/conductive silicon, when it passes through a high temperature process inherent in the process of manufacturing a semiconductor device, respective contact parts of metal and silicon react with each other to form a silicide layer at the interface therebetween. The resistance value of the silicide layer is usually higher than that of metal, thus leading to an increased resistance value of the gate electrode and wiring.
In order to avoid such a silicide layer formation phenomenon, the barrier layer is provided. When W is used for the metal film
6
in
FIG. 12
, the above-mentioned WN
x
film or WSiN film suppresses the mutual diffusion of metal and silicon, and functions as the barrier film
5
. Since the barrier film
5
avoids formation of a silicide layer, the resistance value of the gate electrode and wiring can be maintained low even after passing through the high temperature process.
However, the polymetal gate electrode employing a WN
x
film or WSiN film as a barrier film, has the following drawback that the resistance value between metal and conductive silicon cannot be minimized and the resistance value between metal and conductive silicon is not stable to the current density variation. This will be described by referring to FIG.
13
. As used herein, the term “the resistance value between metal and conductive silicon” is a value obtained by dividing the potential difference between the conductive silicon film
3
and metal film
6
by the current density passing therethrough.
FIG. 13
is a graph showing the result of measurement of the resistance-current density characteristic between metal and conductive silicon in the polymetal gate electrode of FIG.
12
. In
FIG. 13
, the ordinate represents resistance Re and the abscissa represents current density J.
As shown in
FIG. 13
, the resistance value between metal and conductive silicon is approximately 1×10
−5
&OHgr;·cm
2
or more, which cannot be said to be sufficiently low value. This has made it difficult to suppress signal delay due to the resistance between metal and conductive silicon.
Further, as shown in
FIG. 13
, with respect to the current density variation, the resistance value between metal and conductive silicon is unstable and exhibits non-ohmic property. Thus, the gate voltage varies as the current density varies. This has made it difficult to say that the polymetal gate electrode employing a WN
x
film or WSiN film as a barrier film is suited as a gate electrode.
The foregoing drawbacks seem to be due to high resistance of the WN
x
fil

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