Semiconductor device and associated fabrication method

Details Semiconductor device and associated fabrication method Semiconductor device and associated fabrication method

1996-02-14

1998-07-28

Everhart, Caridad

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438638, 438647, 438666, 438672, H01L 2144

Patent

active

057862737

ABSTRACT:
Formed in a second interlayer dielectric are a first contact hole and a second contact hole. The first and second contact holes each extend to a first-level interconnect line. Tungsten is formed on the entirety of a substrate to form a first plug, a second plug, and a tungsten layer. A silicon oxide layer is formed. Thereafter, a patterning process is carried out to form a second-level interconnect line which is connected with the first plug and a top protective layer, and the top of the second plug remains exposed. A sidewall is formed on the side surfaces of the second-level interconnect line and the top protective layer. Subsequently, a third-level interconnect line, which is connected with the exposed second plug, is formed. Such arrangement not only reduces the number of contact hole formation masks, it also cuts down the number of fabrication steps. Further, the aspect ratio of the second contact hole becomes lower thereby achieving highly reliable semiconductor devices.

REFERENCES:
patent: 3880675 (1975-04-01), Tarui et al.
patent: 4990467 (1991-02-01), Lee et al.
patent: 5380679 (1995-01-01), Kano
patent: 5554864 (1996-09-01), Koyama
patent: 5576243 (1996-11-01), Wuu et al.
patent: 5610101 (1997-03-01), Koyama

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