Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1997-06-06
1999-01-19
Yoo, Do Hyun
Static information storage and retrieval
Read/write circuit
Data refresh
365194, 365201, G11C 1300
Patent
active
058620940
ABSTRACT:
According to the present invention, a semiconductor memory device includes an oscillator for generating with a predetermined cycle a timing signal for performing a refresh operation for the memory cell array. The oscillator includes an oscillation circuit, for receiving a predetermined characteristic value and generating the timing signal having the cycle in accordance with the characteristic value; a characteristic value generation circuit, having a programmable memory for generating an adjustment signal for an adjustment of the characteristic value, for transmitting to the oscillation circuit the characteristic value adjusted in accordance with the adjustment signal; and a confirmation switch for generating, instead of the memory, the adjustment signal for a test in accordance with a test entry signal.
REFERENCES:
patent: 5315557 (1994-05-01), Kim et al.
patent: 5532968 (1996-07-01), Lee
patent: 5535169 (1996-07-01), Endo et al.
patent: 5715206 (1998-02-01), Lee et al.
Hatakeyama Atsushi
Kawabata Kuninori
Fujitsu Limited
Yoo Do Hyun
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