Semiconductor device and a method therefor

Details Semiconductor device and a method therefor Semiconductor device and a method therefor

2001-05-26

2003-02-11

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S176000, C438S583000, C257S250000, C257S331000, C257S388000, C257S407000, C257S412000

Reexamination Certificate

active

06518106

ABSTRACT:

FIELD OF THE INVENTION
This invention relates, in general, to semiconductor devices and a method for forming thereof, and, more particularly, to semiconductor devices with dual gates and a method for forming thereof.
BACKGROUND OF THE INVENTION
Polysilicon has traditionally been used as the gate electrode for MOS transistors. The polysilicon electrode is typically doped either P+ or N+ to match the doping of the source and drain regions in CMOS technology. As device dimensions shrink, however, problems exist with using polysilicon as a gate electrode. For example, as the dimensions of the P+ doped polysilicon gate electrode decrease, boron can penetrate from the polysilicon gate electrodes through the gate dielectric and decrease the reliability of the device. In addition, as dimensions shrink for both P+ and N+ doped polysilicon, doping concentrations increase. High temperature processes are performed in order to drive the dopants into the gate electrode. Due to scaling, the source and drain are shallower. Disadvantageously, the high temperature process can cause the source and drain to become deeper. If the high temperature is not performed, however, the dopants are more likely to reside away from the gate dielectric. Hence, there will be an area of the gate electrode that is not doped. This polydepletion effect will act as an additional capacitance in series with the gate dielectric capacitance. In other words, it will undesirably increase the effective oxide thickness of the transistor. The polydepletion effect was not a significant effect in older technology, because the thickness of the polydepletion area was small compared to the gate dielectric effective thickness.
One solution is to use a material which has a work function approximately equal to the work function of either P doped or N doped silicon. P doped silicon has a work function of approximately 4.1 eV whereas N doped silicon has a work function of approximately 5.2 eV. The difficulty is to choose a material which is suitable to both these values. Another option is to use two different materials where one would be approximately equal to the work function of N doped silicon and the other approximately equal to the work function of P doped silicon. It is difficult to find two different materials with different work functions that have the chemical and thermo-stability necessary to be incorporated into a CMOS process flow. Therefore a need exists to find gate materials that are suitable for scaled devices.


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