Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-16
2004-02-03
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S415000, C257S416000, C257S417000, C257S418000, C257S419000, C257S544000, C438S050000, C438S053000, C073S721000, C073S727000
Reexamination Certificate
active
06686634
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and a method of producing the same, and particularly to a semiconductor device for pressure sensor with an integrated circuit and a method of the same.
2. Description of the Prior Art
Semiconductor devices for detecting a pressure with a diaphragm formed by electrochemical etching are known. U.S. Pat. Nos. 5,360,521, 5,525,549, and Japanese patent application provisional application No. 6-45618 disclose this type of semiconductor devices.
More specifically, a semiconductor wafer is prepared which includes a first semiconductor layer (p type silicon layer) having a first conductivity and a second semiconductor layer (n type silicon layer with a second conductivity laminated with the first semiconductor layer. Next, an integrated circuit is formed for each chip unit on the semiconductor wafer. Next, a diaphragm is formed by electrochemical etching at each chip unit. Then, the semiconductor wafer is cut along scribe lines to provide the semiconductor chips.
During this process, on a surface of the semiconductor wafer, a wire of A
1
or the like is formed for electrochemical etching at each chip unit. The first semiconductor layer is partially removed to form a hollow portion to provide the diaphragm by applying a voltage to the wire to effect the electrochemical etching.
In each chip unit, impurity diffusion layers, such as a p
+
impurity diffusion layer, are formed to isolate respective elements in the integrated circuit from each other. The impurity diffusion layer is formed so as to pierce the second semiconductor layer from the surface of the second semiconductor layer opposite to the first semiconductor layer to the surface of the first semiconductor layer contacting the second semiconductor layer.
In these prior arts, the wire for electrochemical etching crosses the impurity diffusion layer. Here, although, the wire is electrically insulated from the impurity diffusion layer with an insulation film such as an oxide film, the wire may short-circuit with the impurity diffusion layer at a crossing point during electrochemical etching because of defects inherently existing the insulation film or the like.
More specifically, during the electrochemical etching, the wire is supplied with a voltage to provide reverse-bias between the first and second semiconductor layers to conduct the etching in the first semiconductor layer. When a current in the wire rapidly increases, etching is finished.
If the wire short-circuits with the impurity diffusion layer at a crossing point or an overlapping point, the current leaks from the wire to the first semiconductor layer through the impurity diffusion layer. Then, the etching is finished at timing of leakage, so that the desired etching cannot be provided.
Thus, it is required to provide a semiconductor device having a diaphragm for pressure detection and an integrated circuit with a structure or a method for preventing short circuit from the etching wire to the first semiconductor layer through the impurity diffusion layer during electrochemical etching.
SUMMARY OF THE INVENTION
The aim of the present invention is to provide a superior semiconductor device and a superior method of producing the same.
According to the present invention, a first aspect of the present invention provides a semiconductor device comprising:
a semiconductor substrate including a first semiconductor layer having a first conductivity and a second semiconductor layer having a second conductivity on said first semiconductor layer, said first semiconductor layer partially having a hollow portion in a first surface opposite to said second semiconductor layer, a surface of said second semiconductor layer opposite to said first semiconductor layer having first and second areas, said first area defined by a thin portion of said semiconductor substrate provided by said hollow portion, said second area being outside said first area;
an integrated circuit portion at said second area;
an impurity diffusion layer with said first conductivity piercing said second semiconductor layer from said surface of said second semiconductor layer to a second surface of said first semiconductor layer contacting said second semiconductor layer, having a width with respect to said surface of said second semiconductor layer, and extending along said surface of said second semiconductor layer for sectioning said second semiconductor layer into a plurality of blocks for isolation;
a wire with first and second ends on said surface of said second semiconductor layer, insulated from said second semiconductor layer except said first end which is connected to said surface of said second semiconductor layer at the inside of said surface, said second end extending to an edge of said semiconductor substrate, said wire being useable for electrochemical etching said first semiconductor layer to form said hollow portion and said thin portion, wherein said wire does not cross said impurity diffusion layer except at said second end.
According to the present invention, a second aspect of the present invention provides the semiconductor device based on the first aspect, wherein said impurity diffusion layer has a C-shaped portion with respect to said surface of said second semiconductor layer substantially surrounding said thin portion, said wire extends to the inside of said C-shaped portion through an opening of said C-shaped portion, and said first end is connected to said second semiconductor layer at said inside of said C-shaped portion.
According to the present invention, a third aspect of the present invention provides the semiconductor device based on the second aspect, wherein said impurity diffusion layer further extends from both ends of said C-shaped portion to a peripheral of said semiconductor substrate in parallel as first and second portions, respectively and further extend along edges of said semiconductor substrate to have an outer C-shape around said C-shape portion, said wire extends from said first end at a space between said first and second portions.
According to the present invention, a fourth aspect of the present invention provides the semiconductor device based on the first aspect, further comprising a diode in said second semiconductor layer, wherein said wire is connected to said second semiconductor layer through said diode to prevent a current from flowing from said second semiconductor layer to said wire.
According to the present invention, a fifth aspect of the present invention provides the semiconductor device based on the first aspect, further comprising an insulation layer on said surface of said second semiconductor layer having a thickness t, said wire being arranged on said insulation layer to be insulated from said second semiconductor layer, a minimum distance between said wire and said impurity diffusion layer is larger than t except the edges of said semiconductor substrate.
According to the present invention, a sixth aspect of the present invention provides the semiconductor device comprising the steps of:
preparing a semiconductor wafer including a first semiconductor layer having a first conductivity and a second semiconductor layer having a second conductivity on said first semiconductor layer;
forming, at each chip unit, an impurity diffusion layer with said first conductivity piercing said second semiconductor layer from an surface of said second semiconductor layer opposite to said first semiconductor layer to a surface of said first semiconductor layer contacting said second semiconductor layer, having a predetermined width with respect to said surface of said second semiconductor layer, and extending along said surface of said second semiconductor layer for sectioning said second semiconductor layer into a plurality of blocks for insulation;
forming an integrated circuit portion on said surface of said second semiconductor layer at each chip unit;
forming, at each chip unit, an wire, at a first end, being connected to said second semiconductor layer at
Denso Corporation
Fahmy Wael
Posz & Bethards, PLC
Rao Shrinivas
LandOfFree
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