Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-04-06
2003-07-01
Potter, Roy (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S700000
Reexamination Certificate
active
06586329
ABSTRACT:
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, and more particularly, to a method of manufacturing a semiconductor device including an insulating layer with a contact hole.
2. Description of the Background Art
The demand of semiconductor devices is rapidly increasing in accordance with the significant spread of information equipment such as computers. Semiconductor devices having a large functional storage capacity and that is capable of operating at high speed are required. In response, technical development is in progress regarding increase in integration density, high speed response and reliability.
A semiconductor device having a multilayer structure where elements and interconnections are formed in a plurality of layers via interlayer insulating films is developed as means for increasing integration density of a semiconductor device. In such a semiconductor device having a multilayer structure, a small contact hole must be formed in the interlayer insulating film to obtain electrical contact between different layers. It has become necessary to form this contact hole in a small dimension and in high accuracy in a narrow space between adjacent elements to comply with the increased scale of integration of semiconductor devices.
The process of forming a contact hole of a memory cell array portion of a DRAM (Dynamic Random Access Memory) will be described hereinafter as an example of forming a conventional contact hole.
A DRAM will first be hereinafter.
FIG. 161
is a block diagram showing a structure of a general DRAM. Referring to
FIG. 161
, a DRAM
1350
includes a memory cell array
1351
, a row and column address buffer
1352
, a row decoder
1353
, a column decoder
1354
, a sense refresh amplifier
1355
, a data-in buffer
1356
, a data-out buffer
1357
, and a clock generator
1358
.
Memory cell array
1351
serves to store data signals of information. Row and column address buffer
1352
serves to receive an externally supplied address signal to select a memory cell forming a unitary storage circuit. Row decoder
1353
and column decoder
1354
serve to specify a memory cell by decoding an address signal. Sense refresh amplifier
1355
amplifies the signal stored in a specified memory cell to read out the same. Data-in buffer
1356
and data-out buffer
1357
serve to input or output data. Clock generator
1358
serves to generate a clock signal.
On a semiconductor chip of a DRAM of the above-described structure, memory cell array
1351
occupies a large area. Memory cell array
1351
has a plurality of memory cells arranged in a matrix for storing unitary storage information.
A memory cell forming memory cell array
1351
will be described hereinafter.
FIG. 162
is an equivalent circuit diagram of 4 bits of memory cells forming memory cell array
1351
. Referring to
FIG. 162
, a memory cell includes one MOS transistor
1310
and one capacitor
1320
connected thereto. Transistor
1310
has its gate electrically connected to a word line
1307
. Transistor
1310
has its source or drain electrically connected to a bit line
1317
. The other of the source/drain of transistor
1310
is connected to capacitor
1320
. This memory cell is a 1-transistor 1-capacitor type memory cell. A memory cell having such a structure facilitates increase of the integration density of a memory cell array due to its simple structure, and is widely used in DRAMs of large capacity.
Next, a conventional contact hole and a method of manufacturing thereof will be described hereinafter.
FIG. 163
is a plan view of a memory cell portion of a DRAM. Referring to
FIG. 163
, word lines (gate electrodes)
203
a
and
203
b
are arranged with a predetermined distance therebetween. A bit line
205
extends in a direction crossing word lines
203
a
and
203
b
. An element formation region
207
is formed to overlie bit line
205
and word lines
203
a
and
203
b
in an oblique manner. A storage node
209
forming the lower electrode of the capacitor is provided in element formation region
207
. Storage node
209
is in direct contact with the semiconductor substrate (not shown) via a contact hole
211
. Bit line
205
is in direct contact with the semiconductor substrate (not shown) via a contact hole
213
.
FIG. 164
is a sectional view of the memory cell portion shown in
FIG. 163
cut in the direction indicated by arrow A. Field oxide films
215
are spaced apart on semiconductor substrate
201
. The main surface of silicon substrate
201
between field oxide films
215
is the element formation region
207
. Impurity regions
217
a
,
217
b
, and
217
c
spaced apart are formed in element formation region
207
. Gate electrodes
203
a
and
203
b
are formed above the main surface-of silicon substrate
201
. A gate oxide film
219
a
is formed between gate electrode
203
a
and silicon substrate
201
. A gate oxide film
219
b
is formed between gate electrode
203
b
and silicon substrate
201
.
An insulating film
221
is formed to cover gate electrodes
203
a
and
203
b
. A TEOS (tetraethyl orthosilicate) film
223
is formed on silicon substrate
201
to cover insulating film
221
. TEOS film
223
has a through hole
213
formed to expose impurity region
217
b
. A bit line
205
is formed on TEOS film
223
. Bit line
205
is electrically connected to impurity region
217
b
via contact hole
213
.
A method of manufacturing the structure shown in
FIG. 163
will be described hereinafter. Referring to
FIG. 165
, field oxide film
215
for element isolation is formed at a predetermined area on the main surface of silicon substrate
201
using the LOCOS (Local Oxidation of Silicon) method. By forming a thin oxide film and then a polycrystalline silicon film on the main surface of silicon substrate
201
followed by a patterning process, gate electrodes
203
a
and
203
b
, and gate oxide films
219
a
and
219
b
are formed. Using gate electrodes
203
a
and
203
b
and field oxide film
215
as a mask, ions are implanted into silicon substrate
201
to form impurity regions
217
a
-
217
c
of relatively low concentration. Insulating film
221
is formed to cover gate electrodes
203
a
and
203
b
. By carrying out ion implantation using insulating film
221
as a mask, impurity regions
217
a
,
217
b
, and
217
c
of relatively high concentration are formed. As a result, impurity regions
217
a
,
217
b
, and
217
c
having a LDD structure are obtained.
As shown in
FIG. 166
, TEOS film
223
is formed all over the main surface of silicon substrate
201
. A stepped portion is generated reflecting the underlying configuration at the surface
223
a
of TEOS film
223
. If a bit line is formed thereabove, it may be disconnected due to the generated stepped portion. A planarization process which will be described hereinafter is carried out to prevent such a problem.
Referring to
FIG. 167
, a SOG (Spin-On Glass) film
225
is formed on TEOS film
223
. SOG film
225
has a low viscosity. Therefore, the surface
223
a
of SOG film
225
is planarized.
Referring to
FIG. 168
, the layer of SOG film
225
and TEOS film
223
is etched back, so that the surface
223
a
of TEOS film
223
is planarized.
Referring to
FIG. 169
, a resist
227
is formed on TEOS film
223
. Resist
227
is exposed and developed to form an opening
227
a
in resist
227
.
Referring to
FIG. 170
, TEOS film
223
is selectively removed by etching using resist
227
as a mask to form a contact hole
213
reaching to impurity region
217
b
. Then, resist
227
is removed. As shown in
FIG. 164
, bit line
205
is formed on TEOS film
223
.
Next, a structure and a manufacturing method of a memory cell in a DRAM to which a conventional contact hole and a manufacturing method thereof is applied will be described hereinafter as conventional first, second and third semiconductor memory devices.
FIG. 171
is a sectional view of a first conventional semiconductor memory device having a stacked capacitor. Referring to
FIG. 171
, a memory cell includes
Akazawa Moriaki
Kasaoka Tatsuo
Kinoshita Mitsuya
Ogawa Toshiaki
Tanaka Yoshinori
Mitsubishi Denki Kabshiki Kaisha
Potter Roy
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