Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1997-04-22
1999-10-12
Wallace, Valencia Martin
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257296, 257306, 257307, 257308, 257309, 257752, 438632, 438698, 438703, 438926, H01L 2348
Patent
active
059659394
ABSTRACT:
A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.
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Ahn Ji-hong
Kim Kyeong-Tae
Park Won-mo
Park Young-hun
Shin Yun-Seung
Martin Wallace Valencia
Samsung Electronics Co,. Ltd.
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