Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
1998-09-15
2003-03-25
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S547000
Reexamination Certificate
active
06537899
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating it, and more particularly to reduction of the number of mask steps in a process of fabricating a power MOSFET, and a structure for suppressing a parasitic capacitance in the power MOSFET which is fabricated in this process.
2. Description of the Related Art
Hereinafter, a power MOSFET of the prior art and a method of fabricating it will be described with reference to the drawings.
FIG. 5
is a section view showing the structure of a power MOSFET of the prior art, and
FIGS. 6
to
8
are section views illustrating a method of fabricating the power MOSFET of the prior art.
In the power MOSFET of the prior art, as shown in
FIG. 5
, a drain layer
1
A consisting of an n
−
epitaxial layer is formed on an n
+
semiconductor substrate
1
, and a channel region
6
is formed in a part of the surface layer of the drain layer by diffusion of a p
−
type impurity. A body region layer
8
is formed at the center of the channel region by diffusing a p
+
impurity. A source region
7
which is formed by diffusion of an n
+
impurity is disposed in the surface layer of the channel region
6
so as to surround the body region layer.
An insulating film
3
is disposed in a region for forming a pad electrode
10
which will be described later.
A gate insulating film
2
and a gate electrode
4
are sequentially formed on the channel region
6
so as to overlap with a part of the channel region
6
and the source region
7
.
A PSG (Phospho-Silicate Glass) film
5
is formed so as to cover the gate electrode
4
. In the PSG film
5
, an opening is formed in a part of the region where the insulating film
3
is formed. The pad electrode
10
for contact to the gate electrode
4
which is exposed through the opening is formed in the opening and in the vicinity thereof. (as shown in
FIG. 5
)
A source electrode wiring (interconnecting layer)
9
for contact to the source region
7
is formed on the source region
7
and the body region
8
.
The steps of fabricating the power MOSFET will be described with reference to
FIGS. 6
to
8
.
First, the n
−
drain layer
1
A is formed on the n
+
semiconductor substrate
1
by epitaxial growth. Next, a thick oxide film is formed on the drain layer, and a resist film is selectively formed by a photolithography process. A patterning process is conducted with using the resist film as a first mask to form the thick insulating film
3
for the pad electrode. Thereafter, an oxide film formed as the gate insulating film
2
is grown. Then, a polycrystalline silicon film
4
A is formed on the entire surface. (See
FIG. 6.
)
Hereinafter, a region where the thick oxide film is formed is referred to as a peripheral region.
Next, a photoresist film is formed on the polycrystalline silicon film
4
A, and then patterned by the photolithography method. The polycrystalline silicon film and the oxide film are etched with using the patterned resist film as a second mask, so that the gate insulating film
2
and the gate electrode
4
are formed as shown in FIG.
7
.
Hereinafter, a region where the gate electrode is formed in a lattice-like shape is referred to as a cell region.
Next, a p
−
type impurity is injected with using the gate insulating film
2
and the gate electrode
4
as a mask, to form the channel region
6
in a part of the surface layer of the drain layer
1
A. (See
FIG. 7.
)
Then, a photoresist (not shown) is again applied to the entire surface, and the third photoresist film is patterned so that the photoresist film in the center portion of the channel region
6
selectively remains. An n
−
type impurity is injected into the channel region
6
with using the photoresist film as a mask, to form the source region
7
. Thereafter, the resist film is removed away. A photoresist is again applied, and then patterned so that an opening is formed in the center portion. Then, a p
−
type impurity is injected into the channel region
6
with using the new resist film (not shown) as a fourth mask, thereby forming the body region
8
. Next, the new resist film is removed away and the PSG film
5
is formed on the entire surface (FIG.
8
).
Thereafter, a resist film (not shown) is formed on the PSG film
5
, and then patterned by the photolithography method so that openings are formed in a peripheral region where the pad electrode will be formed, the body region
8
, and a part of the source region
7
. The PSG film
5
is etched and removed away with using the patterned resist film as a fifth mask. Next, a film of a metal such as aluminum is formed on the entire surface by vapor deposition or the like, and then patterned with using a sixth mask. The source electrode
9
is formed so as to be contacted with the body region
8
and a part of the source region
7
which are exposed as a result of patterning, and the pad electrode
10
is formed on the insulating film
3
. As a result, the power MOSFET having the structure shown in
FIG. 5
is formed.
For the above-described planar type power MOSFET, a photomask for a photolithography process for patterning is required in each of the following steps:
1) the step of forming the mask for forming the initial thick oxide film for the bonding pad,
2) the step of forming the patterning mask for forming the gate electrode (FIG.
7
),
3) the step of forming the resist mask for forming the source region
7
(FIG.
8
),
4) the step of forming the resist mask for forming the body region
8
(FIG.
8
),
5) the step of forming the resist mask in the case where the contact hole of the source region
7
is formed in the PSG film
5
, and
6) the step of forming the resist mask for patterning the pad electrode
10
and the source electrode wiring
9
.
As a result, six photomasks are required in total.
The device isolation step is not included in the above-mentioned steps. A mask is necessary also in the device isolation, and hence a further mask is required.
Therefore, problems in that the number of mask steps and accompanying steps is very large, that the production process is complicated, and that the production cost is high are fabricated.
In the production process of a trench type power MOSFET, a body region and a source region are formed with using a photoresist as a mask. Therefore, the miniaturization is limited and it is difficult to increase the cell density.
SUMMARY OF THE INVENTION
The invention has been conducted in view of the defects of the prior art.
The object of the invention is to provide a power MOSFET Device with a high cell density.
Another object of the invention is to reducing the number of steps in a process fabricating a power MOSFET.
First, the gate insulating film formed below the gate electrode is elongated from the cell region to the peripheral region, whereby a power MOSFET can be obtained without selectively forming a thick insulating film for isolation of a pad electrode with the substrate. The increase of a parasitic capacitance due to the elongation is solved by selectively removing at least a part of one gate electrode located in the peripheral region, and the gate insulating film below the one gate electrode.
When, in order to eliminate the patterning step of the thick oxide film which has been described with reference to
FIG. 6
, the gate insulating film is formed on the entire surface, a parasitic capacitance which uses the gate insulating film as a dielectric is fabricated. However, the increase of the parasitic capacitance can be suppressed by forming the removed region of the gate insulating film in the peripheral region.
Second, the defects can be eliminated by a configuration comprising: an insulating film formed on the gate electrode; a side wall formed on side walls of the lattice-like gate electrode, the gate insulating film below the gate electrode, and the insulating film on the gate electrode; a recess formed in the semiconductor layers surrounded by the side wall; a channel layer of an oppos
Kubo Hirotoshi
Kuwako Eiichiroh
Armstrong Westerman & Hattori, LLP
Loke Steven
Nadav Ori
Sanyo Electric Co,. Ltd.
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