Semiconductor device and a logical circuit formed of the same

Details Semiconductor device and a logical circuit formed of the same Semiconductor device and a logical circuit formed of the same

1977-12-12

1979-03-06

Edlow, Martin H.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 45, 307304, H01L 2702

Patent

active

041433904

ABSTRACT:
A plurality of N-type first regions are formed in matrix arrangement on a P-type semiconductor substrate, and a plurality of N-type second regions are respectively formed on first portions of the P-type semiconductor substrate which are positioned between the N-type first regions along each of the rows of the matrix arrangement. Depletion-type MOS transistors are formed of the second regions each acting as a channel and the N-type first regions disposed on each side of the second regions and acting as a source and a drain, gate electrodes are respectively formed on the second regions and second portions of the P-type semiconductor substrate which are positioned between the second regions, along each of columns of the matrix arrangement of the N-type first regions, and enhancement-type MOS transistors are formed of the second portions of the substrate under the gate electrodes, each of which forms a channel and the second regions disposed on each side of these second portions, which act as a source and drain. That is, the channel regions of the depletion-type MOS transistors function as the source or drain regions of the enhancement-type MOS transistors, the depletion-type MOS transistors and enhancement-type MOS transistors being integrally formed with common regions.

REFERENCES:
patent: 3744036 (1973-07-01), Frohman-Bentchkowsky
patent: 3914855 (1975-10-01), Cheney
patent: 4045811 (1977-08-01), Dingwall
Kawagoe et al., IEEE Journal of Solid State Circuits, vol. Sc-11, No. 3, June 1976.

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