Semiconductor device allowing easy confirmation of operation...

Details Semiconductor device allowing easy confirmation of operation... Semiconductor device allowing easy confirmation of operation...

1999-02-19

2004-07-13

Tran, Khai (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S156000

Reexamination Certificate

active

06763079

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an internal clock generation circuit for generating an internal clock in synchronization with a periodically supplied clock signal.
2. Description of the Background Art
Though an operating speed of a dynamic random access memory (DRAM) employed as a main memory in a system using a memory has been increased, it is still incomparable with that of a micro processor (MPU). It is one reason why an access time and a cycle time of a DRAM is often regarded as a bottle neck causing an overall system performance degradation. To avoid this problem, a Double Data Rate SDRAM (DDR SDRAM) which operates in synchronization with complementary clock signals has recently been proposed as a main memory for fast speed MPU.
In a specification proposed for the DDR SDRAM for allowing access time decrease, four consecutive data per one data input/output terminal, for example, are accessible at a fast speed in synchronization with complementary system clock signals (ext. CLK and ext. /CLK).
FIG. 20
illustrates waveforms showing an operation of the DDR SDRAM upon being accessed.
In this DDR SDRAM, eight-bit data (byte data) can be input/output through data input/output terminals DQ
0
-DQ
7
.
FIG. 20
illustrates operations upon writing and reading of four consecutive data (8×4=32 bits in total). The number of consecutively read data is called a burst length which is changeable by a mode register in the DDR SDRAM.
Operation mode is determined by a combination of states of external control signals /RAS, /CAS and /WE at an edge of the external clock signal ext. CLK. The combination of the states of the external control signals is usually called a command. Here, the external control signal /RAS is a row address strobe signal, the external control signal /CAS is a column address strobe signal and the external control signal /WE is a write enable signal. A signal Add. is an address signal supplied from an external source, a signal DQS is a data strobe signal indicating a timing of receiving/supplying of data and a signal D/Q is a data signal received/supplied via the data input/output terminal.
With reference to
FIG. 20
, at time t
1
, the external control signals /RAS, /CAS and /WE and the address signal Add. are taken in at a rising edge of the clock signal ext. CLK. The address signal Add. is supplied as a row address X and a column address Y multiplexed in a time divisional manner. At the rising edge of the clock signal ext. CLK at t
1
, if the external control signal /RAS is at an “L” (a logical low) which is an active state, an address signal Add. at the time is taken in as a row address Xa.
At time t
2
at a rising edge of the clock signal ext. CLK, if the external control signal CAS is at “L” which is an active state, an address signal Add. at the time is taken in as a column address Yb.
The signals, that is, a command and the address signal are taken in at a rising edge of the ext. CLK. According to the taken row address Xa and column address Yb, a row and a column are selected in the DDR SDRAM.
When a predetermined clock period (3.5 clock cycles in
FIG. 20
) is elapsed at time t
4
after the fall of the external control signal /RAS to “L”, first four data q
0
, q
1
, q
2
and q
3
are supplied as outputs from time t
4
to t
8
. These four data are supplied in synchronization with cross points of the clock signal ext. CLK and the clock signal ext. /CLK.
To enable a fast data transfer, the data strobe signal DQS for notifying a timing of data receipt is supplied as an output in the same phase with the output data.
At time t
3
, overwrite (precharge) of a memory cell is performed, which is performed when the external control signals /RAS and /WE are at “L” at a rising edge of the clock signal ext. CLK.
A writing operation is illustrated from time t
9
onward. A row address Xc is taken at the writing operation in the same manner as at the data reading.
At time t
10
, if the external control signals /CAS and /WE are both at “L” which is an active state at a rising edge of the clock signal ext. CLK, a column address Yd is taken in, and in addition, at time t
11
currently supplied data d
0
is taken in as a first write data.
In other words, in response to falls of external control signals /RAS and /CAS, a column and a row are selected in the DDR SDRAM. From time t
12
to t
14
, input data d
1
, d
2
and d
3
are sequentially taken in synchronization with the data strobe signal DQS and written into the memory cells.
As described in the foregoing, in view of the overall system performance, as a speed of system clock increases along with the increase in the processing speed of MPU, the problem associated with the speed of internal clock signal (int. CLK) cannot be disregarded even in the DDR SDRAM. An internal clock generation circuit is proposed which employs a Delay Locked Loop (hereinafter referred to as DLL) for receiving a clock signal (ext. CLK) which is generated in a semiconductor device or supplied from an external source and generating an internal clock signal (int. CLK) in synchronization with the clock signal.
FIG. 21
is a block diagram showing a configuration of a conventional DLL circuit.
As shown in
FIG. 21
, the conventional DLL circuit includes a clock buffer B
11
receiving an external clock signal ext. CLK supplied from an external source, a phase comparator B
12
comparing a clock signal ECLK and a clock signal RCLK supplied from clock buffer B
11
as outputs and supplying as an output control signals /UP and DOWN according to a phase difference, a charge pump B
13
receiving the control signals /UP and DOWN, a loop filter B
16
receiving an output from charge pump B
13
and supplying as an output control voltage VCOin, a voltage controlling delay circuit B
15
receiving the clock signal ECLK supplied as the output from clock buffer B
11
, delaying it according to control voltage VCOin and supplying as an output the resulting delayed clock ECLK′ and a clock buffer B
14
receiving the delayed clock ECLK′ and supplying the clock signal RCLK and the internal clock signal int. CLK as outputs.
FIG. 22
is a circuit diagram showing a configuration of phase comparator B
12
shown in FIG.
21
.
With reference to
FIG. 22
, phase comparator B
12
includes an inverter B
12
a
receiving and inverting the clock signal ECLK, an NAND circuit B
12
f
receiving an output of inverter B
12
a
and a potential of a node Nl and having its output connected to a node Nf, an NAND circuit B
121
having its inputs connected to nodes Nf, Nr and Ng and its output connected to node Nl, an NAND circuit B
12
g
having its inputs connected to nodes Nf and Nh and its output connected to node Ng, an NAND circuit B
12
h
having its inputs connected to nodes Ng and Nr and its output connected to node Nh and inverters B
12
c
and B
12
d
connected in series, having their input connected to the node Nl and supplying as an output the control signal /UP.
Phase comparator B
12
further includes an inverter B
12
b
receiving the clock signal RCLK, an NAND circuit B
12
k
receiving an output of inverter B
12
b
and a potential of a node Nn and having its output connected to a node Nk, an NAND circuit B
12
m
having its inputs connected to nodes Nj, Nr and Nk and its output connected to node Nn, an NAND circuit B
12
j
having its inputs connected to nodes Ni and Nk and its output connected to node Nj, an NAND circuit B
12
i
having its inputs connected to nodes Nr and Nj and its output connected to node Ni, an NAND circuit B
12
n
having its inputs connected to nodes Ng, Nf, Nk and Nj and its output connected to node Nr and an inverter B
12
e
having its input connected to the node Nn and supplying as an output the control signal DOWN.
FIG. 23
is a circuit diagram showing a configuration of clock buffer B
11
shown in FIG.
21
.
With reference to
FIG. 23
, clock buffer B
11
, including m inverters Ia
1
-Iam (m is a natural number) c

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